EDA技术实验内容交通灯,74ls138,与门等

1．与门

library ieee;

use ieee.std_logic_11.all;

entity and is

port(a,b:in std_logic;

y:out std_logic);

end;

architecture ab of and is

begin

y<=a and b;

end;

2.74LS138译码器

library ieee;

use ieee.std_logic_11.all;

entity 74LS138 is

port(a,b,c:in std_logic;

y:out std_logic_vector(7 downto 0));

end;

architecture art of 74LS138 is

signal data:std_logic_vector(2 downto 0);

begin

data<=c&b&a;

case data is

when \"000\"=>y<=\"11111110\";

when \"001\"=>y<=\"11111101\";

when \"010\"=>y<=\"11111011\";

when \"011\"=>y<=\"11110111\";

when \"100\"=>y<=\"11101111\";

when \"101\"=>y<=\"11011111\";

when \"110\"=>y<=\"10111111\";

when \"111\"=>y<=\"01111111\";

when others=>null;

end case;

end art;

3．计数器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

ENTITY COUNT IS

PORT ( CLK,RST,EN : IN STD_LOGIC ;

CO: OUT STD_LOGIC;

CQ: OUT STD_LOGIC_VECTOR (3DOWNTO 0));

END COUNT;

ARCHITECTURE ONE OF COUNT IS

BEGIN

PROCESS (CLK,RST,EN)

VARIABLE CQ1:STD_LOGIC_VECTOR(3 DOWN TO 0);

BEGIN

IF RST=‘1’ THEN CQ1:=(OTHERS=>‘0’);

ELSIF CLK’EVENT AND CLK=‘1’ THEN

IF EN=‘1’THEN

IF CQ1<15 THEN CQ1:=CQ1+1;

ELSE CQ1:= (OTHERS=>‘0’)

END IF;

END IF;

IF CQ1=15 THEN CO<=‘1’;

ELSE CO<=‘0’;

END IF;

CQ<=CQ1;

END PROCESS;

END ONE;

4扫描显示电路设计

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SCAN_LED IS

PORT ( CLK : IN STD_LOGIC;

SG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --段控制信号输出

BT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );--位控制信号输出

END;

ARCHITECTURE one OF SCAN_LED IS

SIGNAL CNT8 : STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL A : INTEGER RANGE 0 TO 15;

BEGIN

P1：PROCESS( CNT8 )

BEGIN

CASE CNT8 IS

WHEN \"000\" => BT <= \"00000001\" ; A <= 1 ;

WHEN \"001\" => BT <= \"00000010\" ; A <= 3 ;

WHEN \"010\" => BT <= \"00000100\" ; A <= 5 ;

WHEN \"011\" => BT <= \"00001000\" ; A <= 7 ;

WHEN \"100\" => BT <= \"00010000\" ; A <= 9 ;

WHEN \"101\" => BT <= \"00100000\" ; A <= 11 ;

WHEN \"110\" => BT <= \"01000000\" ; A <= 13 ;

WHEN \"111\" => BT <= \"10000000\" ; A <= 15 ;

WHEN OTHERS => NULL ;

END CASE ;

END PROCESS P1;

P2：PROCESS(CLK)

BEGIN

IF CLK'EVENT AND CLK = '1' THEN CNT8 <= CNT8 + 1;

END IF;

END PROCESS P2 ;

P3：PROCESS( A ) –-译码电路

BEGIN

CASE A IS

WHEN 0 => SG <= \"0111111\"; WHEN 2 => SG <= \"1011011\"; WHEN 4 => SG <= \"1100110\"; WHEN 6 => SG <= \"1111101\"; WHEN 8 => SG <= \"1111111\"; WHEN 10 => SG <= \"1110111\"; WHEN 12 => SG <= \"0111001\"; WHEN 14 => SG <= \"1111001\"; WHEN OTHERS => NULL ;

WHEN 1 => SG <= \"0000110\"; WHEN 3 => SG <= \"1001111\"; WHEN 5 => SG <= \"1101101\"; WHEN 7 => SG <= \"0000111\";

WHEN 9 => SG <= \"1101111\"; WHEN 11 => SG <= \"1111100\";

WHEN 13 => SG <= \"1011110\"; WHEN 15 => SG <= \"1110001\";

END CASE ;

END PROCESS P3;

5.正弦信号发生器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

ENTITY sin IS

PORT(clk:IN STD_LOGIC;

DOUT:OUT INTEGER RANGE 255 DOWNTO 0);

END ENTITY sin;

ARCHITECTURE behave OF sin IS

SIGNAL Q:INTEGER RANGE 63 DOWNTO 0;

BEGIN

PROCESS(clk)

BEGIN

IF(CLK'EVENT AND clk='1')THEN

Q<=Q+1;

END IF;

END PROCESS;

PROCESS(Q)

BEGIN

CASE Q IS

WHEN 00=>DOUT<=255;WHEN 01=>DOUT<=254;

WHEN 02=>DOUT<=252;WHEN 03=>DOUT<=249;

WHEN 04=>DOUT<=245;WHEN 05=>DOUT<=239;

WHEN 06=>DOUT<=233;WHEN 07=>DOUT<=225;

WHEN 08=>DOUT<=217;WHEN 09=>DOUT<=207;

WHEN 10=>DOUT<=197;WHEN 11=>DOUT<=186;

WHEN 12=>DOUT<=174;WHEN 13=>DOUT<=162;

WHEN 14=>DOUT<=150;WHEN 15=>DOUT<=137;

WHEN 16=>DOUT<=124;WHEN 17=>DOUT<=112;

WHEN 18=>DOUT<=99;WHEN 19=>DOUT<=87;

WHEN 20=>DOUT<=75;WHEN 21=>DOUT<=;

WHEN 22=>DOUT<=53;WHEN 23=>DOUT<=43;

WHEN 24=>DOUT<=34;WHEN 25=>DOUT<=26;

WHEN 26=>DOUT<=19;WHEN 27=>DOUT<=13;

WHEN 28=>DOUT<=8;WHEN 29=>DOUT<=4;

WHEN 30=>DOUT<=1;WHEN 31=>DOUT<=0;

WHEN 32=>DOUT<=0;WHEN 33=>DOUT<=1;

WHEN 34=>DOUT<=4;WHEN 35=>DOUT<=8;

WHEN 36=>DOUT<=13;WHEN 37=>DOUT<=19;

WHEN 38=>DOUT<=26;WHEN 39=>DOUT<=24;

WHEN 40=>DOUT<=43;WHEN 41=>DOUT<=53;

WHEN 42=>DOUT<=;WHEN 43=>DOUT<=75;

WHEN 44=>DOUT<=87;WHEN 45=>DOUT<=99;

WHEN 46=>DOUT<=112;WHEN 47=>DOUT<=124;

WHEN 48=>DOUT<=137;WHEN 49=>DOUT<=150;

WHEN 50=>DOUT<=162;WHEN 51=>DOUT<=174;

WHEN 52=>DOUT<=186;WHEN 53=>DOUT<=197;

WHEN 54=>DOUT<=207;WHEN 55=>DOUT<=217;

WHEN 56=>DOUT<=225;WHEN 57=>DOUT<=233;

WHEN 58=>DOUT<=239;WHEN 59=>DOUT<=245;

WHEN 60=>DOUT<=249;WHEN 61=>DOUT<=252;

WHEN 62=>DOUT<=254;WHEN 63=>DOUT<=255;

WHEN OTHERS=>NULL;

END CASE;

END PROCESS;

END ARCHITECTURE behave;

6.A/D采样控制电路ADC0809

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

ENTITY adc0809 IS

PORT ( ina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --0809的8位转换数据输出

CLK ,EOC : IN STD_LOGIC; --CLK xitong工作时钟

ALE, ck, OE : OUT STD_LOGIC; --ck是0809de 工作时钟

adda,addb,addc:out std_logic;

outa : OUT STD_LOGIC_VECTOR(13 DOWNTO 0));

END adc0809 ;

ARCHITECTURE behav OF adc0809 IS

signal fp:std_logic_vector(3 downto 0);

signal f:std_logic;

TYPE states IS (st0,st2,st3,st4,st5,st6) ; --定义各状态子类型

SIGNAL current_state, next_state: states :=st0 ;

SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL LOCK : STD_LOGIC; -- 转换后数据输出锁存时钟信号

BEGIN

ADDA <= '0';addb<='0';addc<='0';

process( CLK)

begin

if( CLK'event and CLK='1')then

if fp=\"1100\" then

fp<=\"0000\";

f<=not f;

else

fp<=fp+1;

end if;

end if;

end process;

ck<=f;

PRO: PROCESS(current_state,EOC) BEGIN --规定各状态转换方式

CASE current_state IS

WHEN st0 => ALE<='0';OE<='0';LOCK<='0' ;next_state <= st2;

WHEN st2 => ALE<='1';OE<='0';LOCK<='0' ;next_state <= st3;

WHEN st3 => ALE<='0';OE<='0';LOCK<='0';

IF (EOC='1') THEN next_state <= st3; --测试EOC的下降沿

ELSE next_state <= st4;

END IF ;

WHEN st4=> ALE<='0';OE<='0';LOCK<='0';

IF (EOC='0') THEN next_state <= st4; --测试EOC的上升沿，=1表明转换结束

ELSE next_state <= st5; --继续等待

END IF ;

WHEN st5=> ALE<='0';OE<='1';LOCK<='0';next_state <= st6;

WHEN st6=> ALE<='0';OE<='1';LOCK<='1';next_state <= st0;

WHEN OTHERS => ALE<='0';OE<='0';LOCK<='0';next_state <= st0;

END CASE ;

END PROCESS PRO ;

PROCESS (f)

BEGIN

IF ( f'EVENT AND f='1') THEN

current_state <= next_state; -- 在时钟上升沿，转换至下一状态

END IF;

END PROCESS; -- 由信号current_state将当前状态值带出此进程，进入进程PRO

PROCESS (LOCK) -- 此进程中，在LOCK的上升沿，将转换好的数据锁入

BEGIN

IF LOCK='1' AND LOCK'EVENT THEN REGL <= ina ;

END IF;

END PROCESS ;

with REGL(3 downto 0) select

outa(6 downto 0) <=\"0110000\"when\"0001\

\"1101101\"when\"0010\

\"1111001\"when\"0011\

\"0110011\"when\"0100\

\"1011011\"when\"0101\

\"1011111\"when\"0110\

\"1110000\"when\"0111\

\"1111111\"when\"1000\

\"1111011\"when\"1001\

\"1110111\"when\"1010\

\"0011111\"when\"1011\

\"1001110\"when\"1100\

\"0111101\"when\"1101\

\"1001111\"when\"1110\

\"1000111\"when\"1111\

\"1111110\"when others;--0

with REGL(7 downto 4) select

outa(13 downto 7) <=\"0110000\"when\"0001\

\"1101101\"when\"0010\

\"1111001\"when\"0011\

\"0110011\"when\"0100\

\"1011011\"when\"0101\

\"1011111\"when\"0110\

\"1110000\"when\"0111\

\"1111111\"when\"1000\

\"1111011\"when\"1001\

\"1110111\"when\"1010\

\"0011111\"when\"1011\

\"1001110\"when\"1100\

\"0111101\"when\"1101\

\"1001111\"when\"1110\

\"1000111\"when\"1111\

\"1111110\"when others;--0

END behav;

7.交通灯控制器

计数器的程序

Library Ieee;

Use Ieee.Std_Logic_11.All;

Entity Counter Is

Port

(Clock:In Std_Logic;

Reset:In Std_Logic;

Hold:In Std_Logic;

Countnum: Buffer Integer Range 0 To 49);

End;

Architecture Behavior Of Counter Is

Begin

Process(Reset,Clock)

Begin

If Reset='1' Then

Countnum<=0;

Elsif Rising_Edge(Clock) Then

If Hold='1' Then ——当出现紧急情况时，计数器暂停计数

Countnum<=Countnum;

Else

If Countnum=49 Then

Countnum<=0;

Else

Countnum<=Countnum+1;

End If;

End If;

End If;

End Process;

End;

1控制器的程序

Library Ieee;

Use Ieee.Std_Logic_11.All;

Entity Controller Is

Port

(Clock:In Std_Logic;

Hold:In Std_Logic;

Countnum:In Integer Range 0 To 49; ——前级计数器的计数值

Numa,Numb:Out Integer Range 0 To 25; ——倒计时数值的计数值

Reda,Greena,Yellowa:Out Std_Logic; ——控制东西方向红黄绿灯的亮灭

Redb,Greenb,Yellowb:Out Std_Logic; ——控制南北方向红黄绿灯的亮灭

Flash:Out Std_Logic); ——用以指示七段数码管显示数字的闪烁

End;

Architecture Behavior Of Controller Is

Begin

Process(Clock)

Begin

If Falling_Edge (Clock) Then 取

If Hold='1' Then

Reda<='1';

Redb<='1';

Greena<='0';

Greenb<='0';

Yellowa<='0';

Yellowb<='0';

Flash<='1';

——计数器是上升沿改变计数值，此处下降沿读

Else

Flash<='0';

If Countnum<=19 Then

Numa<=20-Countnum; Reda<='0';

Greena<='1';

Yellowa<='0';

Elsif (Countnum<=24) Then

Numa<=25-Countnum;

Reda<='0';

Greena<='0';

Yellowa<='1';

Else

——计数器东西方向倒计时

Numa<=50-Countnum;

Reda<='1';

Greena<='0';

Yellowa<='0';

End If;

If Countnum<=24 Then 时

Numb<=25-Countnum;

Redb<='1';

Greenb<='0';

Yellowb<='0';

Elsif Countnum<=44 Then

Numb<=45-Countnum;

Redb<='0';

——计数器南北方向倒计

Greenb<='1';

Yellowb<='0';

Else

Numb<=50-Countnum;

Redb<='0';

Greenb<='0';

Yellowb<='1';

End If;

End If;

End If;

End Process;

分位电路程序

Library Ieee;

Use Ieee.Std_Logic_11.All;

Entity Fenwei Is

Port(Numin:In Integer Range 0 To 25;

Numa:Out Integer Range 0 To 2;

Numb:Out Integer Range 0 To 9);

End;

Architecture Behavior Of Fenwei Is

Begin

Process(Numin)

Begin

If Numin>=20 Then

Numa<=2;

Numb<=Numin-20;

Elsif Numin>=10 Then

Numa<=1;

Numb<=Numin-10;

Else

Numa<=0;

Numb<=Numin;

End If;

End Process;

End;

.4.1七段译码电路的程序

Library Ieee;

Use Ieee.Std_Logic_11.All;

Entity Displayone Is

Port(

Clock: In Std_Logic;

Flash: In Std_Logic;

Qin: In Std_Logic_Vector(3 Downto 0);

Display: Out Std_Logic_Vector(0 To 6)

);

End;

Architecture Decoder Of Displayone Is

Signal Timeout:Integer Range 0 To 63;

Begin

Process(Clock)

Begin

If Rising_Edge(Clock) Then

If Flash='0' Then

Timeout<=0;

Else

If Timeout=63 Then

Timeout<=0;

Else

Timeout<=Timeout + 1;

End If;

End If;

If Timeout<31 Then

Case Qin Is

When\"0000\"=>Display<=\"0111111\";

When\"0001\"=>Display<=\"0000110\";

When\"0010\"=>Display<=\"1011011\";

When\"0011\"=>Display<=\"1001111\";

When\"0100\"=>Display<=\"1100110\";

When\"0101\"=>Display<=\"1101101\";

When\"0110\"=>Display<=\"1111101\";

When\"0111\"=>Display<=\"0000111\";

When\"1000\"=>Display<=\"1111111\";

When\"1001\"=>Display<=\"1101111\";

When Others=>Display<=\"0000000\";

End Case;

Else

Display<=\"0000000\";

End If;

End If;

End Process;

End;