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专利名称：Logic circuit design method and logic circuit发明人：Fumio Kasahara申请号：US09775651申请日：20010205公开号：US06518788B2公开日：20030211
专利附图：
摘要：The plurality of flip-flops included in a logic circuit are grouped by the clocksource, thereby judging a relatively large part of the clock skew. Namely, the relativelylarge clock skew generates between the scan flip-flop belonging to a certain groupconnected by the scan path and the scan flip-flop belonging to another group.
Specifically, as the last scan flip-flop of each group is connected to the scan flip-flopbelonging to another group, the scan flip-flop including the delay circuit is applied to thelast scan flip-flop of each group, whereby it is possible to regulate the relatively largeclock skew by use of the less number of basic cells by insertion of the buffer.
申请人：FUJITSU LIMITED
代理机构：Staas & Halsey LLP
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