54ACT166, 74ACT16616-BIT BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTSSCAS127B – MARCH 1990 – REVISED APRIL 1996DMembers of the Texas InstrumentsDDDDDDDDWidebust FamilyInputs Are TTL-Voltage CompatibleIndependent Registers for A and B BusesMultiplexed Real-Time and Stored DataFlow-Through Architecture OptimizesPCB LayoutDistributed VCC and GND Pin ConfigurationMinimizes High-Speed Switching NoiseEPICt (Enhanced-Performance ImplantedCMOS) 1-mm Process500-mA Typical Latch-Up Immunity at125°CPackage Options Include Plastic 300-milShrink Small-Outline (DL) Packages Using25-mil Center-to-Center Pin Spacings and380-mil Fine-Pitch Ceramic Flat (WD)Packages Using 25-mil Center-to-CenterPin Spacings54ACT166...WD PACKAGE74ACT166...DL PACKAGE(TOP VIEW) descriptionThe ’ACT166 are 16-bit bus transceiversconsisting of D-type flip-flops and control circuitrywith 3-state outputs arranged for multiplexedtransmission of data directly from the data bus orfrom the internal storage registers. The devicescan be used as two 8-bit transceivers or one 16-bittransceiver. Data on the A or B bus is clocked intothe registers on the low-to-high transition of theappropriate clock (CLKAB or CLKBA) input.Figure 1 illustrates the four fundamental bus-management functions that can be performedwith the bus transceivers and registers.1DIR1CLKAB1SABGND1A11A2VCC1A31A41A5GND1A61A71A82A12A22A3GND2A42A52A6VCC2A72A8GND2SAB2CLKAB2DIR1234 567101112131415161718192021222324252627285655545352515049484745444342414039383736353433323130291OE1CLKBA1SBAGND1B11B2VCC1B31B41B5GND1B61B71B82B12B22B3GND2B42B52B6VCC2B72B8GND2SBA2CLKBA2OEOutput-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In thetransceiver mode, data present at the high-impedance port may be stored in either register or in both. The selectcontrols (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used forselect control eliminates the typical decoding glitch that occurs in a multiplexer during the transition betweenstored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OEhigh), A data may be stored in one register and/or B data may be stored in the other register.When an output function is disabled, the input function is still enabled and may be used to store and transmitdata. Only one of the two buses, A or B, may be driven at a time.The 74ACT166 is packaged in TI’s shrink small-outline package, which provides twice the functionality ofstandard small-outline packages in the same printed-circuit-board area.The 54ACT166 is characterized for operation over the full military temperature range of –55°C to 125°C. The74ACT166 is characterized for operation from –40°C to 85°C.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.EPIC and Widebus are trademarks of Texas Instruments Incorporated.UNLESS OTHERWISE NOTED this document contains PRODUCTIONDATA information current as of publication date. Products conform tospecifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of allparameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265Copyright © 1996, Texas Instruments Incorporated•1SCAS127B – MARCH 1990 – REVISED APRIL 199654ACT166, 74ACT16616-BIT BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS BUS BOELDIRLCLKABCLKBAXXSABXSBALOELDIRHCLKABXCLKBAXSABLBUS BSBAXREAL-TIME TRANSFERBUS A TO BUS BCLKABXH or LCLKBAH or LXSABXHBUS BSBAHXTRANSFER STORED DATATO A AND/OR BBUS AREAL-TIME TRANSFERBUS B TO BUS ABUS BBUS AOEXXHDIRXXXCLKABCLKBA↑X↑X↑↑SABXXXSBAXXXOELLSTORAGE FROMA, B, OR A AND BFigure 1. Bus-Management Functions2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•BUS ADIRLHBUS A 54ACT166, 74ACT16616-BIT BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTSSCAS127B – MARCH 1990 – REVISED APRIL 1996FUNCTION TABLEINPUTSOEXXHHLLLLDIRXXXXLLHHCLKAB↑X↑H or LXXXH or LCLKBAX↑↑H or LXH or LXXSABXXXXXXLHSBAXXXXLHXXA1–A8InputUnspecifiedInputInputOutputOutputInputInputDATA I/O†B1–B8UnspecifiedInputInputInputInputInputOutputOutputOPERATIONORFUNCTIONOPERATION OR FUNCTIONStore A, B unspecified{Store B, A unspecified{Store A and B dataIsolation, hold storageReal-time B data to A busStored B data to A busReal-time A data to B BusStored A data to bus†The data-output functions may be enabled or disabled by various signals at OE or DIR. Data-input functions are always enabled, i.e., data atthe bus terminals is stored on every low-to-high transition of the clock inputs.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3SCAS127B – MARCH 1990 – REVISED APRIL 199654ACT166, 74ACT16616-BIT BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTSlogic symbol†1OE1DIR1CLKBA1SBA1CLKAB1SAB2OE2DIR2CLKBA2SBA2CLKAB2SAB561555423292830312726G33 EN1 [BA]3 EN2 [AB]C4G5C6G7G1010 EN8 [BA]10 EN9 [AB]C11G12C13G14≥116D1A21A31A41A51A61A71A82A161012131415≥1813D142A22A32A42A52A62A72A8161719202123241141211D121≥19414038373634332B22B32B42B52B62B72B8177551≥1251494847454443421B21B31B41B51B61B71B82B14D521B1 1A15†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.4POST OFFICE BOX 655303 DALLAS, TEXAS 75265• 54ACT166, 74ACT16616-BIT BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTSSCAS127B – MARCH 1990 – REVISED APRIL 1996logic diagram (positive logic)1OE5611DIR551CLKBA541SBA21CLKAB31SABTG1A15TGC11DTG52TG61012131451494847454443B1C11D1A21A31A41A51A61A71A8Seven Channels Identicalto Channel One AboveB2B3B4B5B6B7B82OE292DIR2CLKBA2SBA2CLKAB2SAB28303127262A115TGC11DTGC11DTG42TG1617192021232441403837363433B12A22A32A42A52A62A72A8Seven Channels Identicalto Channel One AboveB2B3B4B5B6B7B8POST OFFICE BOX 655303 DALLAS, TEXAS 75265•5SCAS127B – MARCH 1990 – REVISED APRIL 199654ACT166, 74ACT16616-BIT BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 VInput voltage range, VI (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 VOutput voltage range, VO (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 VInput clamp current, IIK (VI < 0 or VI > VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAOutput clamp current, IOK (VO < 0 or VO > VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAContinuous output current, IO (VO = 0 to VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAContinuous current through VCC or GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mAMaximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 WStorage temperature range, Tstg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.2.The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.recommended operating conditions (see Note 3)54ACT166MINVCCVIHVILVIVOIOHIOLDt/DvSupply voltage (see Note 4)High-level input voltageLow-level input voltageInput voltageOutput voltageHigh-level output currentLow-level output currentInput transition rise or fall rate0–55004.520.8VCCVCC–2424101250–4000MAX5.574ACT166MIN4.520.8VCCVCC–24241085MAX5.5UNITVVVVVmAmAns/V°CTAOperating free-air temperatureNOTES:3.Unused inputs must be held high or low to prevent them from floating.4.All VCC and GND pins must be connected to the proper voltage power supply.PRODUCT PREVIEW information concerns products in the formative ordesign phase of development. Characteristic data and other specificationsare design goals. Texas Instruments reserves the right to change ordiscontinue these products without notice.6POST OFFICE BOX 655303 DALLAS, TEXAS 75265• 54ACT166, 74ACT16616-BIT BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTSSCAS127B – MARCH 1990 – REVISED APRIL 1996electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERTESTCONDITIONSTEST CONDITIONSIOH = –50 =50mAVOH=24mAIOH = –24 mAIOH = –50 mA{IOH = –75 mA{IOL = 50 =50mAVOLIOL = 24 mA=24mAIOL = 50 mA{IOL = 75 mA{IIIOZICCDICCwCiCioControl inputsA or B portsControl inputsA or B ports}VI = VCC or GNDVO = VCC or GNDVI = VCC or GND,IO = 0VCC4.5 V5.5 V4.5 V5.5 V5.5 V5.5 V4.5 V5.5 V4.5 V5.5 V5.5 V5.5 V5.5 V5.5 V5.5 V5.5 V5 V5 V412±0.1±0.580.9±1±1016010.10.10.360.360.10.10.50.51.651.65±1±5801mAmAmAmApFpFTA = 25°CMINTYPMAX4.45.43.944.9454ACT166MIN4.45.43.74.73.853.850.10.10.440.44VMAX74ACT166MIN4.45.43.84.8VMAXUNITOne input at 3.4 V,Other inputs at GND or VCCVI = VCC or GNDVO = VCC or GND†Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.‡For I/O ports, the parameter IOZ includes the input leakage current.§This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.timing requirements over recommended ranges of supply voltage and operating free-airtemperature, (unless otherwise noted) (see Figure 2)TA = 25°CMINMAXfclocktwtsuthClock frequencyPulse duration, CLKAB or CLKBA high or lowSetptimeAbeforeCLKAB↑ or B before CLKBASetup time, A before CLKABorBbeforeCLKBA↑Hold time, A before CLKAB↑ or B before CLKBA↑Data highData low05.5461.59054ACT166MIN05.5461.5MAX9074ACT166MIN05.5461.5MAX90UNITMHznsnsnsPRODUCT PREVIEW information concerns products in the formative ordesign phase of development. Characteristic data and other specificationsare design goals. Texas Instruments reserves the right to change ordiscontinue these products without notice.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•7SCAS127B – MARCH 1990 – REVISED APRIL 199654ACT166, 74ACT16616-BIT BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS switching characteristics over recommended ranges of supply voltage and operating free-airtemperature, (unless otherwise noted) (see Figure 2)PARAMETERfmaxtPLHtPHLtPZHtPZLtPHZtPLZLtPLHtPHLtPLHtPHLtPLHtPHLtPZHtPZLtPHZtPLZFROM(INPUT)TO(OUTPUT)TA = 25°CMINTYPMAX90AorBA or BOEOECLKBAorCLKABCLKBA or CLKABSAB or SBA{(with A or B high)SBA or SAB{(with A or B high)DIRDIRBorAB or AAorBA or BAorBA or BAorBA or BAorBA or BAorBA or BAorBA or BAorBA or B3.93.43.24.25.34.94.95.15.24.94.35.94.54.34.54.47.57.67.797.77.38.9910.38.27.811.29.59.27.97.59.410.610.812.29.69.211.11113.810.69.914.913.611.810.29.854ACT166MIN903.93.43.24.25.34.94.95.15.24.94.35.94.54.34.54.411.512.212.914.610.410.313.113.117.212.512.118.216.214.211.210.8MAX74ACT166MIN903.93.43.24.25.34.94.95.15.24.94.35.94.54.34.54.410.611.411.913.510.29.912.212.315.611.711.116.715.213.110.810.4MAXUNITMHznsnsnsnsnsnsnsns†These parameters are measured with the internal output state of the storage register opposite to that of the bus input.operating characteristics, VCC = 5 V, TA = 25°CPARAMETERCpddPowerdissipationcapacitancepertransceiverPower dissipation capacitance per transceiverOutputs enabledOutputs disabledTEST CONDITIONSCL = 50 pF,=50pFf=1MHzf = 1 MHzTYP5813UNITpFPRODUCT PREVIEW information concerns products in the formative ordesign phase of development. Characteristic data and other specificationsare design goals. Texas Instruments reserves the right to change ordiscontinue these products without notice.8POST OFFICE BOX 655303 DALLAS, TEXAS 75265• 54ACT166, 74ACT16616-BIT BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTSSCAS127B – MARCH 1990 – REVISED APRIL 1996PARAMETER MEASUREMENT INFORMATION2 × VCCFrom Output Under TestCL = 50 pF(see Note A)500 ΩS1OpenGND500 ΩTESTtPLH/tPHLtPLZ/tPZLtPHZ/tPZHS1Open2 × VCCGNDLOAD CIRCUITTiming Inputtw3 VInput1.5 V1.5 V0 VVOLTAGE WAVEFORMSOutputControl(low-levelenabling)OutputWaveform 1S1 at 2 × VCC(see Note B)OutputWaveform 2S1 at GND(see Note B)tPZHVOLTAGE WAVEFORMSData Inputtsu1.5 V3 V1.5 V0 Vth3 V1.5 V0 V3 VInput1.5 VtPLHIn-PhaseOutputtPHLOut-of-PhaseOutput50% VCC50% VCC1.5 V0 VtPHLVOH50% VCCVOLtPLHVOH50% VCCVOL3 V1.5 VtPZLtPLZ50% VCCtPHZ80% VCCVOH[ 0 V20% VCC[ VCCVOL1.5 V0 V50% VCCVOLTAGE WAVEFORMSVOLTAGE WAVEFORMSNOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics:PRR ≤ 1 MHz, ZO = 50 Ω, tr =3 ns, tf = 3 ns.D.The outputs are measured one at a time with one input transition per measurement.Figure 2. Load Circuit and Voltage WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•9PACKAGEOPTIONADDENDUM
www.ti.com
18-Jul-2006
PACKAGINGINFORMATION
OrderableDevice74ACT166DL74ACT166DLG474ACT166DLR74ACT166DLRG4
(1)
Status(1)ACTIVEACTIVEACTIVEACTIVE
PackageTypeSSOPSSOPSSOPSSOP
PackageDrawingDLDLDLDL
PinsPackageEcoPlan(2)
Qty56565656
2020
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU
MSLPeakTemp(3)Level-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIM
1000Green(RoHS&
noSb/Br)1000Green(RoHS&
noSb/Br)
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
Addendum-Page1
PACKAGEMATERIALSINFORMATION
www.ti.com
11-Mar-2008
TAPEANDREELINFORMATION
*Alldimensionsarenominal
Device
PackagePackagePinsTypeDrawingSSOP
DL
56
SPQ
ReelReelDiameterWidth(mm)W1(mm)330.0
32.4
A0(mm)B0(mm)K0(mm)
P1(mm)16.0
WPin1(mm)Quadrant32.0
Q1
74ACT166DLR100011.3518.673.1
PackMaterials-Page1
PACKAGEMATERIALSINFORMATION
www.ti.com
11-Mar-2008
*Alldimensionsarenominal
Device74ACT166DLR
PackageType
SSOP
PackageDrawing
DL
Pins56
SPQ1000
Length(mm)
346.0
Width(mm)346.0
Height(mm)
49.0
PackMaterials-Page2
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 MECHANICAL DATA DL (R-PDSO-G**) 48 PINS SHOWN0.025 (0,635)PLASTIC SMALL-OUTLINE PACKAGE0.0135 (0,343)0.008 (0,203)250.005 (0,13)M480.010 (0,25)0.005 (0,13)0.299 (7,59)0.291 (7,39)0.420 (10,67)0.395 (10,03)Gage Plane0.010 (0,25)1A240°–ā8°0.040 (1,02)0.020 (0,51)Seating Plane0.110 (2,79) MAX0.008 (0,20) MIN0.004 (0,10)PINS **DIMA MAX280.380(9,65)0.370(9,40)480.630(16,00)0.620(15,75)560.730(18,54)0.720(18,29)4040048/E 12/01A MINNOTES:A.B.C.D.All linear dimensions are in inches (millimeters).This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).Falls within JEDEC MO-118POST OFFICE BOX 655303 DALLAS, TEXAS 75265•IMPORTANTNOTICE
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