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专利名称：PHASE LOCKED LOOP AND OPERATING
METHOD THEREOF
发明人：Ja Yol LEE,Minjae LEE,Cheon Soo
KIM,Jaehyun KANG,Minuk HEO
申请号：US15184113申请日：20160616
公开号：US20160373121A1公开日：20161222
专利附图：
摘要：Provided is a phase locked loop (PLL) that generates an output clock signalcorresponding to a reference clock signal. The phase locked loop (PLL) includes a divider
configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulsecorresponding to a phase difference between the reference clock signal and the dividedclock signal, and a digitally controlled oscillator including an LC resonance circuit forgenerating the output clock signal and configured to control a frequency of the outputclock signal that is determined to correspond to a time constant of the LC resonancecircuit according to the time-pulse conversion signal, wherein a sustainment time ofchanged capacitance is continuously controlled according to a change in the phasedifference between the reference clock signal and the divided clock signal.
申请人：ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
地址：Daejeon KR
国籍：KR
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