SC16C750BIB-S资料

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SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

Rev. 05 — 17 October 2008

Product data sheet

1.General description

TheSC16C750BisaUniversalAsynchronousReceiverandTransmitter(UART)usedforserial data communications. Its principal function is to convert parallel data into serialdata, and vice versa. The UART can handle serial data rates up to 3Mbit/s.

The SC16C750B is pin compatible with the TL16C750 and it will power-up to befunctionally equivalent to the 16C450. Programming of control registers enables the

addedfeaturesoftheSC16C750B.Someoftheseaddedfeaturesarethe-bytereceiveand transmit FIFOs, automatic hardware ﬂow control. The selectable auto-ﬂow controlfeature signiﬁcantly reduces software overload and increases system efﬁciency while inFIFO mode by automatically controlling serial data ﬂow usingRTS output andCTS inputsignals. The SC16C750B also provides DMA mode data transfers through FIFO triggerlevels and theTXRDY andRXRDY signals. On-board status registers provide the userwith error indications, operational status, and modem interface control. System interruptsmay be tailored to meet user requirements. An internal loopback capability allowson-board diagnostics.

TheSC16C750Boperatesat5V,3.3Vand2.5V,theindustrialtemperaturerangeandisavailable in plastic PLCC44, LQFP, and HVQFN32 packages.

2.Features

IIIIIIIIIII

Single channel

5V, 3.3V and 2.5V operation5V tolerant on input only pins1

Industrial temperature range (−40°C to +85°C)

After reset, all registers are identical to the typical 16C450 register setCapable of running with all existing generic 16C450 software

Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,PC16C450/550. Software compatible with SC16C750 and TL16C750

Upto3Mbit/stransmit/receiveoperationat5V,2Mbit/sat3.3V,and1Mbit/sat2.5V-byte transmit FIFO

-byte receive FIFO with error ﬂagsProgrammable auto-RTS and auto-CTSNIn auto-CTS mode,CTS controls transmitterNIn auto-RTS mode, receive FIFO contents and threshold controlRTSAutomatic hardware ﬂow control

Software selectable baud rate generator

For data bus pins D7 to D0, seeTable 24 “Limiting values”.

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

IIIIIII

Four selectable Receive interrupt trigger levelsStandard modem interfaceSleep mode

Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)Independent receiver clock input

Transmit, Receive, Line Status, and data set interrupts independently controlledFully programmable character formatting:N5-bit, 6-bit, 7-bit, or 8-bit charactersNEven, odd, or no-parity formatsN1, 11⁄2, or 2-stop bit

NBaud generation (DC to 3Mbit/s)False start-bit detection

Complete status reporting capabilities

3-state output TTL drive capabilities for bidirectional data bus and control busLine break generation and detectionInternal diagnostic capabilities:

NLoopback controls for communications link fault isolationPrioritized interrupt system controls

Modem control functions (CTS,RTS,DSR,DTR,RI,DCD)3.Ordering information

Table 1.Ordering information

Industrial: VCC=2.5V, 3.3V or 5V±10%; Tamb=−40°C to +85°C.Type numberSC16C750BIA44SC16C750BIBSC16C750BIBS

PackageNamePLCC44LQFPHVQFN32

Descriptionplastic leaded chip carrier; 44 leadsplastic low proﬁle quad ﬂat package; leads; 10×10×1.4mmplastic thermal enhanced very thin quad ﬂat package; no leads;32terminals; body 5×5×0.85mm

VersionSOT187-2SOT314-2SOT617-1

Product data sheetRev. 05 — 17 October 20082 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

4.Block diagram

SC16C750BTRANSMITFIFOREGISTERSTRANSMITSHIFTREGISTERTXD0 to D7IOR, IORIOW, IOWRESETDATA BUSANDCONTROLLOGICFLOWCONTROLLOGICINTERCONNECT BUS LINESANDCONTROL SIGNALSRECEIVEFIFOREGISTERSRECEIVESHIFTREGISTERRXA0 to A2CS0, CS1, CS2ASREGISTERSELECTLOGICFLOWCONTROLLOGICDDISDTRRTSOUT1, OUT2MODEMCONTROLLOGICINTTXRDYRXRDYINTERRUPTCONTROLLOGICCLOCK ANDBAUD RATEGENERATORCTSRIDCDDSR002aaa588XTAL1RCLKXTAL2BAUDOUTShown for PLCC44 and LQFP pin assignments.Fig 1.Block diagram of SC16C750BSC16C750B_5© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 05 — 17 October 20083 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

5.Pinning information

5.1Pinning

42DCD41DSR40CTS39RESET38OUT137DTR36RTS35OUT234n.c.33INT32RXRDY31A030A129A2XTAL118XTAL219IOW20IOW21GND22n.c.23IOR24IOR25DDIS26TXRDY27AS2818A017A1XTAL210IOW11n.c.12GND13IOR14TXRDY15A2169002aaa5D5D6D77RCLK10RX11n.c.12TX13CS014CS115CS216BAUDOUT17SC16C750BIA44Fig 2.Pin conﬁguration for PLCC4426DSR44VCC43RI27VCC654321n.c.D4D3D2D1D032D431D330D229D1D5D6D7RCLKRXTXCSBAUDOUT1234567828D0terminal 1index area25CTS24RESET23OUT22DTR21RTS20INT19RXRDY002aaa949SC16C750BIBSXTAL1Transparent top viewFig 3.Pin conﬁguration for HVQFN32SC16C750B_5© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 05 — 17 October 20084 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

BAUDOUT54RCLK62CS261CS159CS063n.c.60n.c.57n.c.56n.c.53n.c.XTAL1XTAL2n.c.IOWn.c.IOWn.c.GNDIOR123456749n.c.55RX58TX52D751D650D548D447n.c.46D345D244n.c.43D142D041n.c.40VCC39n.c.38RI37n.c.36DCD35DSR34n.c.33CTSSC16C750BIBIOR10n.c.11DDIS12TXRDY13n.c.14AS15n.c.16A217A118n.c.19A020RXRDY21n.c.22INT23n.c.24OUT225RTS26n.c.27DTR28n.c.29OUT130n.c.31RESET32002aaa590Fig 4.Pin conﬁguration for LQFP5.2Pin description

Table 2.SymbolPin descriptionPinPLCC44LQFPA2, A1, A029, 30,31AS2817, 18, 20HVQFN3216, 17, 18IRegister select. A0 to A2 are used during read and writeoperations to select the UART register to read from or write to.Refer toTable3 for register addresses and refer toAS description.Address strobe. WhenAS is active (LOW), A0, A1, and A2 andCS0,CS1,andCS2drivetheinternalselectlogicdirectly;whenASis HIGH, the register select and chip select signals are held at thelogic levels they were in when the LOW-to-HIGH transition ofASoccurred.Baud out.BAUDOUT is a 16× clock signal for the transmittersection of the UART. The clock rate is established by the referenceoscillator frequency divided by a divisor speciﬁed in the baud rategenerator divisor latches.BAUDOUT may also be used for thereceiver section by tying this output to RCLK.Chipselect.WhenCS0andCS1areHIGHandCS2isLOW,thesethreeinputsselecttheUART.Whenanyoftheseinputsareinactive,the UART remains inactive (refer toAS description).TypeDescription15-IBAUDOUT178OCS0,CS1,14, 15,CS216CS-59, 61, 62--7IISC16C750B_5© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 05 — 17 October 20085 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

Table 2.SymbolCTSPin description …continuedPinPLCC44LQFP4033HVQFN3225IClear to send.CTS is a modem status signal. Its condition can bechecked by reading bit4 (CTS) of the Modem Status Register(MSR). MSR[3] (∆CTS) indicates thatCTS has changed statessince the last read from the MSR. If the modem status interrupt isenabled whenCTS changes levels and the auto-CTS mode is notenabled, an interrupt is generated.CTS is also used in theauto-CTS mode to control the transmitter.Data bus. Eight data lines with 3-state outputs provide abidirectional path for data, control and status information betweenthe UART and the CPU.Data carrier detect.DCD is a modem status signal. Its conditioncan be checked by reading bit7 (DCD) of the Modem StatusRegister (MSR). MSR[3] (∆DCD) indicates thatDCD has changedstates since the last read from the MSR. If the modem statusinterrupt is enabled whenDCD changes levels, an interrupt isgenerated.Driver disable.DDIS is active (LOW) when the CPU is readingdata. When inactive (HIGH),DDIS can disable an externaltransceiver.Datasetready.DSRisamodemstatussignal.Itsconditioncanbecheckedbyreadingbit5(DSR)oftheModemStatusRegister.Bit1(DDSR) of the MSR indicatesDSR has changed levels since thelast read from the MSR. If the modem status interrupt is enabledwhenDSR changes levels, an interrupt is generated.Data terminal ready. When active (LOW),DTR informs a modemordatasetthattheUARTisreadytoestablishcommunication.DTRis placed in the active level by setting theDTR bit of the ModemControl Register.DTR is placed in the inactive level either as aresult of a Master Reset, during Loopback mode operation, orclearing theDTR bit.Interrupt.Whenactive(HIGH),INTinformstheCPUthattheUARThas an interrupt to be serviced. Four conditions that cause aninterrupt to be issued are: a receiver error, received data that isavailable or timed out (FIFO mode only), an empty transmitterholding register or an enabled modem status interrupt. INT is reset(deactivated)eitherwhentheinterruptisservicedorasaresultofaMaster Reset.not connectedTypeDescriptionD7 to D09, 8, 7,6, 5, 4,3, 24252,51,50,3,2,1,32,I/O48,46,45,31, 30,43, 4229, 2836-IDCDDDIS2612-ODSR413526IDTR372822OINT332320On.c.343,5,7,11,1214,16,19,22,24,27,29,31,34,37,39,41,44,47,49,53,56,57,60, 6330, 25--23-OUT1,OUT2OUT38, 35-OOOutputs 1 and 2. These are user-designated output terminals thatare set to the active (LOW) level by setting respective ModemControl Register (MCR) bits (OUT1 andOUT2).OUT1 andOUT2are set to inactive the (HIGH) level as a result of Master Reset,during Loopback mode operations, or by clearing bit2 (OUT1) orbit3 (OUT2) of the MCR.© NXP B.V. 2008. All rights reserved.

SC16C750B_5

Product data sheetRev. 05 — 17 October 20086 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

Table 2.SymbolRCLKRESETIORIORPin description …continuedPinPLCC44LQFP103925245432109HVQFN32424-14IIIIReceiver clock. RCLK is the 16× baud rate clock for the receiversection of the UART.Master Reset. When active (HIGH), RESET clears most UARTregisters and sets the levels of various output signals.Read inputs. When eitherIOR or IOR is active (LOW or HIGH,respectively) while the UART is selected, the CPU is allowed toreadstatusinformationordatafromaselectedUARTregister.Onlyoneoftheseinputsisrequiredforthetransferofdataduringareadoperation; the other input should be tied to its inactive level (that is,IOR tied LOW orIOR tied HIGH).Ring indicator.RI is a modem status signal. Its condition can bechecked by reading bit6 (RI) of the Modem Status Register. Bit2(∆RI) of the MSR indicates thatRI has changed from a LOW to aHIGH level since the last read from the MSR. If the modem statusinterrupt is enabled when this transition occurs, an interrupt isgenerated.Request to send. When active,RTS informs the modem or dataset that the UART is ready to receive data.RTS is set to the activelevel by setting theRTS Modem Control Register bit and is set tothe inactive (HIGH) level either as a result of a Master Reset orduring Loopback mode operations or by clearing bit 1 (RTS) of theMCR. In the auto-RTS mode,RTS is set to the inactive level by thereceiver threshold control logic.Receiver ready. Receiver Direct Memory Access (DMA) signalingisavailablewithRXRDY.WhenoperatingintheFIFOmode,oneoftwotypesofDMAsignalingcanbeselectedusingtheFIFOControlRegister bit3 (FCR[3]). When operating in the 16C450 mode, onlyDMA mode0 is allowed. Mode 0 supports single-transfer DMA inwhich a transfer is made between CPU bus cycles. Mode 1supports multi-transfer DMA in which multiple transfers are madecontinuously until the receiver FIFO has been emptied. In DMAmode 0 (FCR[0]=0 or FCR[0]=1, FCR[3]=0), when there is atleastonecharacterinthereceiverFIFOorreceiverholdingregister,RXRDY is active (LOW). WhenRXRDY has been active but thereare no characters in the FIFO or holding register,RXRDY goesinactive (HIGH). In DMA mode1 (FCR[0]=1, FCR[3]=1), whenthe trigger level or the time-out has been reached,RXRDY goesactive (LOW); when it has been active but there are no morecharacters in the FIFO or holding register, it goes inactive (HIGH).Serial data input. RX is serial data input from a connectedcommunications device.Serial data output. TX is composite serial data output to aconnected communication device. TX is set to the marking (HIGH)level as a result of Master Reset.TypeDescriptionRI4338-IRTS362621ORXRDY322119ORXTX1113555856IOSC16C750B_5© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 05 — 17 October 20087 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

Table 2.SymbolTXRDYPin description …continuedPinPLCC44LQFP2713HVQFN3215OTransmitter ready. Transmitter DMA signaling is available withTXRDY. When operating in the FIFO mode, one of two types ofDMA signaling can be selected using FCR[3]. When operating inthe 16C450 mode, only DMA mode0 is allowed. Mode0 supportssingle-transfer DMA in which a transfer is made between CPU buscycles. Mode1 supports multi-transfer DMA in which multipletransfers are made continuously until the transmit FIFO has beenﬁlled.TypeDescriptionVCCGNDIOWIOW442221204082713-11Power2.5V, 3V or 5V supply voltage.PowerGround voltage.IIWrite inputs. When eitherIOW or IOW is active (LOW or HIGH,respectively)andwhiletheUARTisselected,theCPUisallowedtowritecontrolwordsordataintoaselectedUARTregister.Onlyoneof these inputs is required to transfer data during a write operation;the other input should be tied to its inactive level (that is, IOW tiedLOW orIOW tied HIGH).Crystal connection or External clock input.Crystal connection or the inversion of XTAL1 if XTAL1 isdriven.XTAL1XTAL2[1]181912910IO[1]In Sleep mode, XTAL2 is left ﬂoating.

6.Functional description

TheSC16C750B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiversections.Thesefunctionsarenecessaryforconvertingtheserialdatastreamintoparallel data that is required with digital data systems. Synchronization for the serial datastream is accomplished by adding start and stop bits to the transmit data to form a datacharacter(characterorientatedprotocol).Dataintegrityisinsuredbyattachingaparitybitto the data character. The parity bit is checked by the receiver for any transmission biterrors. TheSC16C750B is fabricated with an advanced CMOS process to achieve lowdrain power and high speed requirements.

TheSC16C750B is an upward solution that provides bytes of transmit and receiveFIFO memory, instead of none in the 16C450, or 16bytes in the 16C550. TheSC16C750B is designed to work with high speed modems and shared network

environmentsthatrequirefastdataprocessingtime.IncreasedperformanceisrealizedintheSC16C750B by the larger transmit and receive FIFOs. This allows the externalprocessor to handle more networking tasks within a given time. In addition, the four

selectablelevelsofFIFOtriggerinterruptandautomatichardwareﬂowcontrolisuniquelyprovided for maximum data throughput performance, especially when operating in a

multi-channel environment. The combination of the above greatly reduces the bandwidthrequirement of the external controlling CPU, increases performance, and reduces powerconsumption.

TheSC16C750Biscapableofoperationupto3Mbit/switha48MHzexternalclockinput(at 5V).

SC16C750B_5

Product data sheetRev. 05 — 17 October 20088 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

The rich feature set of theSC16C750B is available through internal registers. Automatichardware ﬂow control, selectable transmit and receive FIFO trigger level, selectable TXand RX baud rates, modem interface controls, and a sleep mode are some of thesefeatures.

6.1Internal registers

TheSC16C750Bprovides12internalregistersformonitoringandcontrol.Theseregistersare shown inTable3. These twelve registers are similar to those already available in thestandard16C550.Theseregistersfunctionasdataholdingregisters(THR/RHR),interruptstatus and control registers (IER/ISR), a FIFO Control Register (FCR), line status andcontrol registers (LCR/LSR), modem status and control registers (MCR/MSR),

programmable data rate (clock) control registers (DLL/DLM), and a user accessibleScratchpad Register (SPR). Register functions are more fully described in the followingparagraphs.

Table 3.A20000111100

[1][2]

Internal registers decodingA10011001100

A00101010101

READ modeReceive Holding RegisterInterrupt Enable RegisterInterrupt Status RegisterLine Control RegisterModem Control RegisterLine Status RegisterModem Status RegisterScratchpad RegisterLSB of Divisor LatchMSB of Divisor Latch

WRITE modeTransmit Holding RegisterInterrupt Enable RegisterFIFO Control RegisterLine Control RegisterModem Control Registern/an/a

Scratchpad RegisterLSB of Divisor LatchMSB of Divisor Latch

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]Baud rate register set (DLL/DLM)[2]

These registers are accessible only when LCR[7] is a logic0.These registers are accessible only when LCR[7] is a logic1.

Product data sheetRev. 05 — 17 October 200 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

6.2FIFO operation

The -byte transmit and receive data FIFOs are enabled by the FIFO Control Registerbit0 (FCR[0]). The receiver FIFO section includes a time-out function to ensure data isdelivered to the external CPU. An interrupt is generated whenever the Receive HoldingRegister (RHR) has not been read following the loading of a character or the receivetrigger level has not been reached.

Table 4.

Flow control mechanism

INT pin activationNegateRTSAssertRTSSelected trigger level(characters)16-byte FIFO14814

-byte FIFO1163256

148141163256

00000000

6.3Hardware ﬂow control

Whenautomatichardwareﬂowcontrolisenabled,theSC16C750BmonitorstheCTSpinfor a remote buffer overﬂow indication and controls theRTS pin for local buffer overﬂows.Automatic hardware ﬂow control is selected by setting MCR[5] (RTS) and MCR[1] (CTS)to a logic1. IfCTS transitions from a logic0 to a logic1 indicating a ﬂow control request,theSC16C750BwillsuspendTXtransmissionsassoonasthestopbitofthecharacterinprocess is shifted out. Transmission is resumed after theCTS input returns to a logic0,indicating more data may be sent.

With the auto-RTS function enabled, an interrupt is generated when the receive FIFOreaches the programmed trigger level. TheRTS pin will not be forced to a logic1 (RTSoff),untilthereceiveFIFOreachesthenexttriggerlevel.However,theRTSpinwillreturnto a logic0 after the data buffer (FIFO) is emptied. However, under the above describedconditions, the SC16C750B will continue to accept data until the receive FIFO is full.

6.4Time-out interrupts

When two interrupt conditions have the same priority, it is important to service theseinterrupts correctly. Receive Data Ready and Receive Time-Out have the same interruptpriority (when enabled by IER[0]). The receiver issues an interrupt after the number ofcharacters have reached the programmed trigger level. In this case, theSC16C750BFIFOmayholdmorecharactersthantheprogrammedtriggerlevel.Followingtheremovalof a data byte, the user should re-check LSR[0] for additional characters. A ReceiveTime-Out will not occur if the receive FIFO is empty. The time-out counter is reset at thecenter of each stop bit received or each time the receive holding register (RHR) is read.The actual time-out value is 4 character time.

Product data sheetRev. 05 — 17 October 200810 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

6.5Programmable baud rate generator

TheSC16C750B supports high speed modem technologies that have increased inputdata rates by employing data compression schemes. For example, a 33.6kbit/s modemthat employs data compression may require a 115.2kbit/s input data rate. A128.0kbit/sISDNmodemthatsupportsdatacompressionmayneedaninputdatarateof460.8kbit/s.A single baud rate generator is provided for the transmitter and receiver, allowing

independentTX/RXchannelcontrol.Theprogrammablebaudrategeneratoriscapableofaccepting an input clock up to 48MHz, as required for supporting a 3Mbit/s data rate.TheSC16C750B can be conﬁgured for internal or external clock operation. For internalclock oscillator operation, an industry standard microprocessor crystal (parallel resonant,22pF to 33pF load) is connected externally between the XTAL1 and XTAL2 pins (seeFigure5). Alternatively, an external clock can be connected to the XTAL1 pin to clock theinternal baud rate generator for standard or custom rates (seeTable5).

XTAL1XTAL2XTAL1XTAL21.5 kΩX11.8432 MHzC122 pFC233 pFX11.8432 MHzC122 pFC247 pF002aaa870Fig 5.Crystal oscillator connectionThe generator divides the input 16× clock by any divisor from 1 to (216−1). TheSC16C750B divides the basic crystal or external clock by 16. The frequency of theBAUDOUT output pin is exactly 16× (16 times) of the selected baud rate

(BAUDOUT=16Baud Rate). Customized baud rates can be achieved by selecting theproper divisor values for the MSB and LSB sections of baud rate generator.

Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides auser capability for selecting the desired ﬁnal baud rate. The example inTable5 showsselectable baud rates when using a 1.8432MHz crystal.

For custom baud rates, the divisor value can be calculated usingEquation1:XTAL1clockfrequency

divisor(indecimal)=----------------------------------------------------------------serialdatarate×16

(1)

Product data sheetRev. 05 — 17 October 200811 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

Baud rates using 1.8432MHz or 3.072MHz crystal

Using 3.072MHz crystalBaud rateerrorDesiredbaudrate50750.0260.058110134.5150300600120018000.6920002400360048007200960019200384002.86Divisor for16× clock3840256017451428128003201601079680534027201051.230.6280.3120.0260.034Baud rateerrorDivisor for16× clock23041536104785776838419296584832241612632Table 5.Desiredbaudrate5075110134.515030060012001800200024003600480072009600192003840056000Using 1.8432MHz crystal6.6DMA operation

TheSC16C750B FIFO trigger level provides additional ﬂexibility to the user for blockmode operation. The user can optionally operate the transmit and receive FIFOs in theDMA mode (FCR[3]). The DMA mode affects the state of theRXRDY andTXRDY outputpins.Table6 andTable7 show this.

Table 6.

Effect of DMA mode on state ofRXRDY pinDMA mode0-to-1 transition when FIFO empties

1-to-0 transition when FIFO reaches trigger level,ortime-out occurs

Non-DMA mode1=FIFO empty

0=at least 1 byte in FIFO

Table 7.Effect of DMA mode on state ofTXRDY pinDMA mode0-to-1 transition when FIFO becomes full1-to-0 transition when FIFO becomes empty

Non-DMA mode1=at least 1 byte in FIFO0=FIFO empty

Product data sheetRev. 05 — 17 October 200812 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

6.7Sleep mode

TheSC16C750B is designed to operate with low power consumption. A special Sleepmode is included to further reduce power consumption (the internal oscillator driver isdisabled) when the chip is not being used. With IER[4] enabled (set to a logic1), theSC16C750B enters the Sleep mode, but resumes normal operation when a start bit isdetected,achangeofstateofRXoronanyofthemodeminputpinsRI,CTS,DSR,DCD,or a transmit data is provided by the user. If the Sleep mode is enabled and the

SC16C750B is awakened by one of the conditions described above, it will return to theSleepmodeautomaticallyafterthelastcharacteristransmittedorreadbytheuser.Inanycase, the Sleep mode will not be entered while an interrupt(s) is pending. The

SC16C750BwillstayintheSleepmodeofoperationuntilitisdisabledbysettingIER[4]toa logic0.

6.8Low power mode

In Low power mode the oscillator is still running and only the clock to the UART core iscutoff.Thishelpstoreducetheoperatingcurrenttoabout1⁄3.TheUARTwakesupunderthe same conditions as in Sleep mode.

6.9Loopback mode

The internal loopback capability allows on-board diagnostics. In the Loopback mode, thenormal modem interface pins are disconnected and reconﬁgured for loopback internally.MCR[3:0] register bits are used for controlling loopback diagnostic testing. In the

Loopbackmode,OUT1andOUT2intheMCRregister(bit2andbit3)controlthemodemRI andDCD inputs, respectively. MCR signalsDTR andRTS (bit0 and bit1) are used tocontrolthemodemDSRandCTSinputs,respectively.Thetransmitteroutput(TX)andthereceiverinput(RX)aredisconnectedfromtheirassociatedinterfacepins,andinsteadareconnected together internally (seeFigure6). TheCTS,DSR,DCD, andRI aredisconnected from their normal modem control input pins, and instead are connectedinternallytoRTS,DTR,OUT2andOUT1.LoopbacktestdataisenteredintotheTransmitHolding Register via the user data bus interface, D0toD7. The transmit UART serializesthe data and passes the serial data to the receive UART via the internal loopback

connection.ThereceiveUARTconvertstheserialdatabackintoparalleldatathatisthenmade available at the user data interface D0toD7. The user optionally compares thereceived data to the initial transmitted data for verifying error-free operation of the UARTTX/RX circuits.

Product data sheetRev. 05 — 17 October 200813 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

SC16C750BTRANSMITFIFOREGISTERSTRANSMITSHIFTREGISTERTXD0 to D7IOR, IORIOW, IOWRESETDATA BUSANDCONTROLLOGICFLOWCONTROLLOGICMCR[4] = 1INTERCONNECT BUS LINESANDCONTROL SIGNALSRECEIVEFIFOREGISTERSRECEIVESHIFTREGISTERRXA0 to A2CS0, CS1, CS2ASREGISTERSELECTLOGICFLOWCONTROLLOGICRTSDDISCTSDTRINTTXRDYRXRDYINTERRUPTCONTROLLOGICCLOCK ANDBAUD RATEGENERATORMODEMCONTROLLOGICDSROUT1RIOUT2DCD002aaa591XTAL1RCLKXTAL2BAUDOUTShown for PLCC44 and LQFP pin assignments.Fig 6.Internal Loopback mode diagramSC16C750B_5© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 05 — 17 October 200814 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

7.Register descriptions

Table8detailstheassignedbitfunctionsfortheﬁfteenSC16C750Binternalregisters.Theassigned bit functions are more fully deﬁned inSection7.1 throughSection7.10.

Table 8.

SC16C750B internal registers

Bit 6bit 6bit 60Bit 5bit 5bit 5Lowpowermode-byteFIFOenable-byteFIFOenableBit 4bit 4bit 4SleepmodeBit 3bit 3bit 3modemstatusinterruptDMAmodeselectINTprioritybit2parityenableOUT2Bit 2bit 2bit 2receivelinestatusinterruptXMITFIFOresetINTprioritybit1stop bitsBit 1bit 1bit 1transmitholdingregisterRCVRFIFOresetINTprioritybit0wordlengthbit1RTSBit 0bit 0bit 0receiveholdingregisterFIFOenableINTstatuswordlengthbit0DTRA2A1A0RegisterDefault[1]Bit 7General Register Set[2]000000001RHRTHRIERXXXX00bit 7bit 70010FCR00RCVRtrigger(MSB)FIFOsenableddivisorlatchenable0RCVRtrigger(LSB)FIFOsenabledreserved010ISR010011LCR00set breaksetparity0ﬂowcontrolenabletrans.holdingemptyDSRbit 5bit 5bit 13evenparityloopback100MCR00OUT1101LSR60FIFOdataerrorDCDbit 7bit 7bit 15trans.emptyRIbit 6bit 6bit 14breakinterruptCTSbit 4bit 4bit 12framingerror∆DCDbit 3bit 3bit 11parityerror∆RIbit 2bit 2bit 10overrunerror∆DSRbit 1bit 1bit 9receivedataready∆CTSbit 0bit 0bit 81100[1][2][3]

11000101MSRSPRDLLDLMX0FFXXXXSpecial Register Set[3]The value shown represents the register’s initialized HEX value; X=n/a.These registers are accessible only when LCR[7]=0.

The Special Register set is accessible only when LCR[7] is set to a logic1.

Product data sheetRev. 05 — 17 October 200815 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

7.1TransmitHoldingRegister(THR)andReceiveHoldingRegister(RHR)

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) andTransmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register(LSR).WritingtotheTHRtransfersthecontentsofthedatabus(D7toD0)totheTHR,providingthattheTHRorTSRisempty.TheTHRemptyﬂagintheLSRregisterwillbe set to a logic1 when the transmitter is empty or when data is transferred to the TSR.Note that a write operation can be performed when the THR empty ﬂag is set(logic0=FIFO full; logic1=at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR).Receive data is removed from theSC16C750B and receive FIFO by reading the RHRregister. The receive section provides a mechanism to prevent false starts. On the fallingedge of a start or false start bit, an internal receiver counter starts counting clocks at the16× clock rate. After 71⁄2 clocks, the start bit time should be shifted to the center of thestart bit. At this time the start bit is sampled, and if it is still a logic0 it is validated.Evaluating the start bit in this manner prevents the receiver from assembling a falsecharacter. Receiver status codes will be posted in the LSR.

7.2Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitterempty, line status and modem status registers. These interrupts would normally be seenon the INT output pin.

Table 9.Bit7:65

Interrupt Enable Register bits description

DescriptionNot used.Low power mode.

logic0=disable Low power mode (normal default condition)logic1=enable Low power mode

IER[4]

Sleep mode.

logic0=disable Sleep mode (normal default condition)

logic1=enable Sleep mode. SeeSection 6.7 “Sleep mode” for details.3IER[3]Modem Status Interrupt.logic0=disable the modem status register interrupt (normal defaultcondition)

logic1=enable the modem status register interrupt

IER[2]

Receive Line Status interrupt. This interrupt will be issued whenever a fullyassembled receive character is transferred from RSR to the RHR/FIFO, i.e.,data ready, LSR[0].

logic0=disable the receiver line status interrupt (normal default condition)logic1=enable the receiver line status interrupt

SymbolIER[7:6]IER[5]

Product data sheetRev. 05 — 17 October 200816 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

Interrupt Enable Register bits description …continuedDescriptionTransmit Holding Register interrupt. This interrupt will be issued whenever theTHR is empty, and is associated with LSR[1].

logic0=disable the transmitter empty interrupt (normal default condition)logic1=enable the transmitter empty interrupt

Table 9.Bit1SymbolIER[1]0IER[0]

ReceiveHoldingRegisterinterrupt.ThisinterruptwillbeissuedwhentheFIFOhas reached the programmed trigger level, or is cleared when the FIFO dropsbelow the trigger level in the FIFO mode of operation.

logic0=disable the receiver ready interrupt (normal default condition)logic1=enable the receiver ready interrupt

7.2.1IER versus Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0]=logic1), and receive interrupts (IER[0]=logic1) areenabled, the receive interrupts and register status will reﬂect the following:

•The receive data available interrupts are issued to the external CPU when the FIFO

has reached the programmed trigger level. It will be cleared when the FIFO dropsbelow the programmed trigger level.

•FIFO status will also be reﬂected in the user accessible ISR register when the FIFO

trigger level is reached. Both the ISR register status bit and the interrupt will becleared when the FIFO drops below the trigger level.

•The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift

7.2.2IER versus Receive/Transmit FIFO polled mode operation

When FCR[0]=logic1, resetting IER[3:0] enables theSC16C750B in the FIFO polledmode of operation. Since the receiver and transmitter have separate bits in the LSR,either or both can be used in the polled mode by selecting respective transmit or receivecontrol bit(s).

•••••

LSR[0] will be a logic1 as long as there is onebyte in the receive FIFO.LSR[4:1] will provide the type of errors encountered, if any.LSR[5] will indicate when the transmit FIFO is empty.

LSR[6]willindicatewhenboththetransmitFIFOandtransmitshiftregisterareempty.LSR[7] will indicate any FIFO data errors.

Product data sheetRev. 05 — 17 October 200817 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

7.3FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO triggerlevels, and select the DMA mode.

7.3.1DMA mode

7.3.1.1

Mode 0 (FCR bit 3=0)

Setandenabletheinterruptforeachsingletransmitorreceiveoperation,andissimilartothe 16C450 mode. Transmit Ready (TXRDY) will go to a logic0 whenever an emptytransmit space is available in the Transmit Holding Register (THR). Receive Ready

(RXRDY)willgotoalogic0whenevertheReceiveHoldingRegister(RHR)isloadedwitha character.

7.3.1.2

Mode 1 (FCR bit 3=1)

Setandenabletheinterruptinablockmodeoperation.ThetransmitinterruptissetwhenthetransmitFIFOisbelowtheprogrammedtriggerlevel.Thereceiveinterruptissetwhenthe receive FIFO ﬁlls to the programmed trigger level. However, the FIFO continues to ﬁllregardlessoftheprogrammedleveluntiltheFIFOisfull.RXRDYremainsalogic0aslongas the FIFO ﬁll level is above the programmed trigger level.

7.3.2FIFO mode

Table 10.Bit7:6FIFO Control Register bits description

DescriptionRCVR trigger. These bits are used to set the trigger level for the receiveFIFO interrupt.

AninterruptisgeneratedwhenthenumberofcharactersintheFIFOequalstheprogrammedtriggerlevel.However,theFIFOwillcontinuetobeloadeduntil it is full. Refer toTable11.-byte FIFO enable.logic0=16-byte mode (normal default condition)logic1=-byte mode

FCR[4]FCR[3]

reserved

DMA mode select.

logic0=set DMA mode ‘0’ (normal default condition).logic1=set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C750B is in the 16C450mode (FIFOs disabled; FCR[0]=logic0) or in the FIFO mode (FIFOsenabled; FCR[0]=logic1; FCR[3]=logic0), and when there are no

charactersinthetransmitFIFOortransmitholdingregister,theTXRDYpinwill be a logic0. Once active, theTXRDY pin will go to a logic1 after theﬁrst character is loaded into the transmit holding register.

Receive operation in mode ‘0’: When the SC16C750B is in 16C450

mode,orintheFIFOmode(FCR[0]=logic1;FCR[3]=logic0)andthereisat least one character in the receive FIFO, theRXRDY pin will be a logic0.Once active, theRXRDY pin will go to a logic1 when there are no morecharacters in the receiver.

SymbolFCR[7](MSB),

FCR[6] (LSB)

Product data sheetRev. 05 — 17 October 200818 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

FIFO Control Register bits description …continuedDescriptionTransmit operation in mode ‘1’: When the SC16C750B is in FIFO mode(FCR[0]=logic1; FCR[3]=logic1), theTXRDY pin will be a logic1 whenthe transmit FIFO is completely full. It will be a logic0 when the FIFO isemptied.

Receive operation in mode ‘1’: When the SC16C750B is in FIFO mode(FCR[0]=logic1;FCR[3]=logic1)andthetriggerlevelhasbeenreached,or a Receive Time-Out has occurred, theRXRDY pin will go to a logic0.Once activated, it will go to a logic1 after there are no more characters inthe FIFO.

Table 10.BitSymbolFCR[3](continued)

2FCR[2]XMIT FIFO reset.

logic0=no FIFO transmit reset (normal default condition)

logic1=clears the contents of the transmit FIFO and resets the FIFOcounterlogic(thetransmitshiftregisterisnotclearedoraltered).Thisbitwill return to a logic0 after clearing the FIFO.

1FCR[1]RCVR FIFO reset.

logic0=no FIFO receive reset (normal default condition)

logic1=clears the contents of the receive FIFO and resets the FIFOcounter logic (the receive shift register is not cleared or altered). This bitwill return to a logic0 after clearing the FIFO.

0FCR[0]FIFO enable.

logic0=disable the transmit and receive FIFO (normal default condition)logic1=enable the transmit and receive FIFO

Table 11.FCR[7]0011

RCVR trigger levels

FCR[6]0101

RX FIFO trigger level (bytes)16-byte operation14814

-byte operation1163256

Product data sheetRev. 05 — 17 October 200819 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

7.4Interrupt Status Register (ISR)

TheSC16C750Bprovidesfourlevelsofprioritizedinterruptstominimizeexternalsoftwareinteraction.TheInterruptStatusRegister(ISR)providestheuserwithfourinterruptstatusbits. Performing a read cycle on the ISR will provide the user with the highest pendinginterrupt level to be serviced. No other interrupts are acknowledged until the pendinginterrupt is serviced. Whenever the interrupt status register is read, the interrupt status iscleared. However, it should be noted that only the current pending interrupt is cleared bythe read. A lower level interrupt may be seen after re-reading the interrupt status bits.Table 12 “Interrupt source” shows the data values (bit0tobit4) for the four prioritizedinterrupt levels and the interrupt sources associated with each of these interrupt levels.

Table 12.Prioritylevel12234Table 13.Bit7:6Interrupt sourceISR[3]00100

ISR[2]11100

ISR[1]10010

ISR[0]00000

Source of the interruptLSR (Receiver Line Status Register)RXRDY (Received Data Ready)RXRDY (Receive Data time-out)

TXRDY (Transmitter Holding Register Empty)MSR (Modem Status Register)

Interrupt Status Register bits descriptionSymbolISR[7:6]DescriptionFIFOs enabled. These bits are set to a logic0 when the FIFO is notbeing used. They are set to a logic1 when the FIFOs are enabled.logic0 or cleared=default condition-byte FIFO enable.logic0=16-byte operationlogic1=-byte operation

5ISR[5]

43:1

ISR[4]ISR[3:1]

not used

INT priority bit2tobit0. These bits indicate the source for a pendinginterrupt at interrupt priority levels 1, 2, and 3 (seeTable12).logic0 or cleared=default conditionINT status.

logic0=an interrupt is pending and the ISR contents may be usedas a pointer to the appropriate interrupt service routinelogic1=no interrupt pending (normal default condition)

0ISR[0]

Product data sheetRev. 05 — 17 October 200820 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

7.5Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format.Thewordlength,thenumberofstopbits,andtheparityareselectedbywritingtheappropriate bits in this register.

Table 14.Bit7Line Control Register bits description

DescriptionDivisor latch enable. The internal baud rate counter latch and EnhancedFeature mode enable.

logic0=divisor latch disabled (normal default condition)logic1=divisor latch and enhanced feature register enabled

LCR[6]

Set break. When enabled, the Break control bit causes a break condition tobetransmitted(theTXoutputisforcedtoalogic0state).Thisconditionexistsuntil disabled by setting LCR[6] to a logic0.

logic0=no TX break condition (normal default condition)

logic1=forces the transmitter output (TX) to a logic0 for alerting theremote receiver to a line break condition

LCR[5]

Set parity. If the parity bit is enabled, LCR[5] selects the forced parity format.Programs the parity conditions (seeTable15).

logic0=parity is not forced (normal default condition)

LCR[5]=logic1andLCR[4]=logic0:paritybitisforcedtoalogic1forthetransmit and receive data

LCR[5]=logic1andLCR[4]=logic1:paritybitisforcedtoalogic0forthetransmit and receive data

LCR[4]

Even parity. If the parity bit is enabled with LCR[3] set to a logic1, LCR[4]selects the even or odd parity format.

logic0=oddparityisgeneratedbyforcinganoddnumberoflogic1sinthetransmitted data. The receiver must be programmed to check the sameformat (normal default condition).

logic1=even parity is generated by forcing an even number of logic1s inthetransmitteddata.Thereceivermustbeprogrammedtocheckthesameformat.

LCR[3]

Parity enable. Parity or no parity can be selected via this bit.logic0=no parity (normal default condition)

logic1=a parity bit is generated during the transmission, receiver checksthe data and parity for transmission errors

LCR[2]

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with theprogrammed word length (seeTable16).logic0 or cleared=default condition

1:0

LCR[1:0]

Word length bit1, bit0. These two bits specify the word length to betransmitted or received (seeTable17).logic0 or cleared=default condition

Product data sheetRev. 05 — 17 October 200821 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

LCR[5] parity selectionLCR[4]X0101

LCR[3]01111

Parity selectionno parityodd parityeven parityforce parity ‘1’forced parity ‘0’

Table 15.LCR[5]X0011Table 16.LCR[2]011Table 17.LCR[1]0011

LCR[2] stop bit lengthWord length (bits)5, 6, 7, 856, 7, 8

LCR[1:0] word lengthLCR[0]0101

Word length (bits)5678

Stop bit length (bit times)111⁄22

Product data sheetRev. 05 — 17 October 200822 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

7.6Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 18.Bit7654

Modem Control Register bits description

Descriptionreserved; set to 0reserved; set to 0

AFE. This bit is the auto ﬂow control enable. When this bit is set, the autoﬂow control is enabled.

Loopback. Enable the local Loopback mode (diagnostics). In this mode thetransmitteroutput(TX)andthereceiverinput(RX),CTS,DSR,DCD,andRIaredisconnectedfromtheSC16C750BI/Opins.Internallythemodemdataand control pins are connected into a loopback data conﬁguration (seeFigure6). In this mode, the receiver and transmitter interrupts remain fullyoperational. The Modem Control Interrupts are also operational, but theinterrupts’sourcesareswitchedtothelowerfourbitsoftheModemControl.Interrupts continue to be controlled by the IER register.logic0=disable Loopback mode (normal default condition)logic1=enable local Loopback mode (diagnostics)

3MCR[3]OUT2,INTenable.UsedtocontrolthemodemDCDsignalintheLoopbackmode.

logic0=setOUT2 to HIGH. In the Loopback mode, setsOUT2 (DCD)internally to a logic1.

logic1=setOUT2 to LOW. In the Loopback mode, setsOUT2 (DCD)internally to a logic0.

21MCR[2]MCR[1]OUT1. This bit is used in the Loopback mode only. In the Loopback mode,thisbitisusedtowritethestateofthemodemRIinterfacesignalviaOUT1.RTSlogic0=forceRTS output to a logic1 (normal default condition)logic1=forceRTS output to a logic0

0MCR[0]DTRlogic0=forceDTR output to a logic1 (normal default condition)logic1=forceDTR output to a logic0

SymbolMCR[7]MCR[6]MCR[5]MCR[4]

The ﬂow control can be conﬁgured by programming MCR[1] and MCR[5] as shown inTable19.

Table 19.110Flow control conﬁguration

Product data sheetRev. 05 — 17 October 200823 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

7.7Line Status Register (LSR)

This register provides the status of data transfers between theSC16C750B and theCPU.

Table 20.Bit7Line Status Register bits description

DescriptionFIFO data error.logic0=no error (normal default condition)

logic1=at least one parity error, framing error or break indication is in thecurrent FIFO data. This bit is cleared when LSR register is read.

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to alogic1 whenever the transmit holding register and the transmit shift register arebothempty.Itisresettologic0whenevereithertheTHRorTSRcontainsadatacharacter.IntheFIFOmode,thisbitissettologic1wheneverthetransmitFIFOand transmit shift register are both empty.

THR empty. This bit is the Transmit Holding Register Empty indicator. This bitindicates that the UART is ready to accept a new character for transmission. Inaddition, this bit causes the UART to issue an interrupt to CPU when the THRinterrupt enable is set. The THR bit is set to a logic1 when a character is

transferred from the transmit holding register into the transmitter shift register.The bit is reset to a logic0 concurrently with the loading of the transmitter

holding register by the CPU. In the FIFO mode, this bit is set when the transmitFIFO is empty; it is cleared when at least 1byte is written to the transmit FIFO.Break interrupt.

logic0=no break condition (normal default condition)

logic1=the receiver received a break signal (RX was a logic0 for one

character frame time). In the FIFO mode, only one break character is loadedinto the FIFO.

LSR[3]

Framing error.

logic0=no framing error (normal default condition)

logic1=framingerror.Thereceivecharacterdidnothaveavalidstopbit(s).Inthe FIFO mode, this error is associated with the character at the top of theFIFO.

LSR[2]

Parity error.

logic0=no parity error (normal default condition)

logic1=parity error. The receive character does not have correct parity

informationandissuspect.IntheFIFOmode,thiserrorisassociatedwiththecharacter at the top of the FIFO.

LSR[1]

Overrun error.

logic0= no overrun error (normal default condition)

logic1=overrun error. A data overrun error occurred in the receive shiftregister. This happens when additional data arrives while the FIFO is full. Inthiscase,thepreviousdataintheshiftregisterisoverwritten.Notethatunderthis condition, the data byte in the receive shift register is not transferred intothe FIFO, therefore the data in the FIFO is not corrupted by the error.

LSR[0]

Receive data ready.

logic0= no data in receive holding register or FIFO (normal default condition)logic1=datahasbeenreceivedandissavedinthereceiveholdingregisterorFIFO

SymbolLSR[7]5LSR[5]

4LSR[4]

Product data sheetRev. 05 — 17 October 200824 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

7.8Modem Status Register (MSR)

Thisregisterprovidesthecurrentstateofthecontrolinterfacesignalsfromthemodem,orother peripheral device to which theSC16C750B is connected. Fourbits of this registerare used to indicate the changed information. These bits are set to a logic1 whenever acontrolinputfromthemodemchangesstate.Thesebitsaresettoalogic0whenevertheCPU reads this register.

Table 21.Bit7Modem Status Register bits description

DescriptionData Carrier Detect. DCD (activeHIGH, logic1). Normally this bit is thecomplement of theDCD input. In the Loopback mode this bit is equivalent tothe OUT2 bit in the MCR register.

Ring Indicator. RI (activeHIGH, logic1). Normally this bit is the complementof theRI input. In the Loopback mode this bit is equivalent to the OUT1 bit inthe MCR register.

Data Set Ready. DSR (activeHIGH, logic1). Normally this bit is the

complement of theDSR input. In Loopback mode this bit is equivalent to theDTR bit in the MCR register.

Clear To Send. CTS.CTS functions as hardware ﬂow control signal input if itis enabled via MCR[5]. Flow control (when enabled) allows starting andstopping the transmissions based on the external modemCTS signal. Alogic1attheCTSpinwillstopSC16C750Btransmissionsassoonascurrentcharacter has ﬁnished transmission. Normally MSR[4] is the complement oftheCTS input. However, in the Loopback mode, this bit is equivalent to theRTS bit in the MCR register.∆DCD[1]logic0= noDCD change (normal default condition)logic1=theDCDinputtotheSC16C750Bhaschangedstatesincethelasttime it was read. A modem Status Interrupt will be generated.

2MSR[2]∆RI[1]logic0= noRI change (normal default condition)logic1=theRI input to the SC16C750B has changed from a logic0 to alogic1. A modem Status Interrupt will be generated.

1MSR[1]∆DSR[1]logic0= noDSR change (normal default condition)logic1=theDSRinputtotheSC16C750Bhaschangedstatesincethelasttime it was read. A modem Status Interrupt will be generated.

0MSR[0]∆CTS[1]logic0= noCTS change (normal default condition)logic1=theCTSinputtotheSC16C750Bhaschangedstatesincethelasttime it was read. A modem Status Interrupt will be generated.

[1]

Whenever any MSR[0:3] is set to logic1, a Modem Status Interrupt will be generated.

SymbolMSR[7]6MSR[6]

5MSR[5]

Product data sheetRev. 05 — 17 October 200825 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

7.9Scratchpad Register (SPR)

TheSC16C750B provides a temporary data register to store 8bits of user information.

7.10SC16C750B external reset conditions

Table 22.RegisterIERISRLCRMCRLSRMSRFCRTable 23.OutputTXRTSDTRRXRDYTXRDYINT

Reset state for registers

Reset stateIER[7:0]=0ISR[7:1]=0; ISR[0]=1LCR[7:0]=0MCR[7:0]=0

LSR[7]=0; LSR[6:5]=1; LSR[4:0]=0MSR[7:4]=input signals; MSR[3:0]=0FCR[7:0]=0

Reset state for outputs

Reset stateHIGHHIGHHIGHHIGH (STD mode)LOW (STD mode)LOW (STD mode)

8.Limiting values

Table 24.Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).SymbolVCCVnTambTstgPtot/pack

Parametersupply voltagevoltage on any other pinambient temperaturestorage temperaturetotal power dissipationperpackage

at D7 to D0 pinsat input only pinsoperatingConditionsMin-GND−0.3GND−0.3−40−65-Max7VCC+0.35.3+85+150500

UnitVVV°C°CmW

Product data sheetRev. 05 — 17 October 200826 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

9.Static characteristics

Table 25.Static characteristics

Tamb=−40°C to +85°C; tolerance of VCC=±10%, unless otherwise speciﬁed.SymbolVIL(clk)VIH(clk)VILVIHVOL

Parameterclock LOW-level input voltageclock HIGH-level input voltageLOW-level input voltageHIGH-level input voltageLOW-level output voltage

on all outputsIOL=5mA(databus)IOL=4mA(other outputs)IOL=2mA(databus)IOL=1.6mA(other outputs)

VOH

HIGH-level output voltage

IOH=−5mA(databus)IOH=−1mA(other outputs)IOH=−800µA(databus)IOH=−400µA(other outputs)

ILILIL(clk)ICC(AV)ICC(sleep)ICC(lp)CiRpu(int)

[1][2]

[1]

ConditionsVCC=2.5VMin−0.31.8−0.31.6------1.851.85---[2]

VCC=3.3VMin−0.32.4−0.32.0-----2.0--------500

Max0.6VCC0.8--0.4------±10±304.5501.55-

VCC=5.0VMin−0.53.0−0.52.2----2.4---------500

Max0.6VCC0.8VCC0.4-------±10±304.5501.55-

UnitVVVVVVVVVVVVµAµAmAµAmApFkΩ

Max0.45VCC0.65---0.40.4----±10±303.5501.05-

LOW-level input leakage currentclock leakage currentaverage supply currentsleep mode supply currentlow-power mode supply currentinput capacitanceinternal pull-up resistance

---500

Except for XTAL2, VOL=1V typically.

Sleep current might be higher if there is activity on the UART databus during Sleep mode.

Product data sheetRev. 05 — 17 October 200827 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

10.Dynamic characteristics

Table 26.Dynamic characteristics

Tamb=−40°C to +85°C; tolerance of VCC=±10%, unless otherwise speciﬁed.Symboltw1tw2fXTAL1t4wt5st5ht6st6ht6s't6ht7dt7wt7ht7h't8dt9dt11dt12dt12ht13dt13wt13ht14dt15dt16st16ht17dt18dt19dt20dt21dt22dt23d

Parameterclock pulse durationclock pulse durationfrequency on pin XTAL1address strobe widthaddress set-up timeaddress hold time

chip select set-up time toASaddress hold timeaddress set-up timechip select hold timeIOR delay from chip selectIOR strobe widthchip select hold time fromIORaddress hold timeIOR delay from addressread cycle delayIOR toDDIS delaydelay fromIOR to datadata disable time

IOW delay from chip selectIOW strobe widthchip select hold time fromIOWIOW delay from addresswrite cycle delaydata set-up timedata hold time

delay fromIOW to outputdelay to set interrupt fromModem input

delay to reset interrupt fromIORdelay from stop to set interruptdelay fromIOR to resetinterrupt

delay from start to set interruptdelay fromIOW to transmitstart

[3][2][2][1]

ConditionsVCC=2.5VMin1515-455510010010Max--16-------------1007715-------1001001001TRCLK100100

VCC=3.3VMin1313-3555501001026051020---102001025205------Max--32-------------352615-------3324241TRCLK2945

VCC=5.0VMin1010-251500501023051020---101501020155------Max--48-------------302315-------2923231TRCLK2840

UnitnsnsMHznsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnssnsns

25pF load77051020---1020010252015

25pF load25pF load25pF load25pF load

25pF load25pF load25pF load

[3]

------

Product data sheetRev. 05 — 17 October 200828 of 44

NXP Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

Table 26.Dynamic characteristics …continuedTamb=−40°C to +85°C; tolerance of VCC=±10%, unless otherwise speciﬁed.Symbolt24dt25dt26dt27dt28dtRESETN

[1][2][3][4]

Parameterdelay fromIOW to resetinterrupt

delay from stop to setRXRDYdelay fromIOR to resetRXRDYdelay fromIOW to setTXRDYdelay from start to resetTXRDYReset pulse widthbaud rate divisor

ConditionsVCC=2.5VMin-[3]VCC=3.3VMin-----401

Max451TRCLK45458TRCLK

-216−1

VCC=5.0VMin-----401

Max401TRCLK40408TRCLK

-216−1

Unitnssnsnssns

Max1001TRCLK1001008TRCLK

-216−1

---[3]

-1001

[4]

Applies to external clock, crystal oscillator max 24MHz.Applicable only whenAS is tied LOW.RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.Reset pulse must happen when these signals are inactive:CS,CS2, CS1, CS0, IOR,IOR, IOW,IOW.10.1Timing diagrams

t4wASt5svalidaddresst6sCS2CS1, CS0t7dt8dIOR, IORt11dt6ht5hA0 to A2validt7wactivet7ht9dt11hactiveDDISt12dD0 to D7t12hdata002aaa331Fig 7.General read timing when usingAS signalSC16C750B_5© NXP B.V. 2008. All rights reserved.

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t4wASt5svalidaddresst6sCS2CS1, CS0t13dt14dIOW, IOWt6ht5hA0 to A2validt13wt13ht15dactivet16st16hD0 to D7data002aaa332Fig 8.General write timing when usingAS signalA0 to A2t6s'validaddresst7h'activet7wactivet12dt12ht9dt6s'validaddresst7wactivet7h'CSIORt12dt12hD0 to D7data002aaa333Fig 9.General read timing whenAS is tied to GNDSC16C750B_5© NXP B.V. 2008. All rights reserved.

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5 V, 3.3 V and 2.5 V UART with -byte FIFOs

A0 to A2t6s'validaddresst7h't6s'validaddresst7h'CSactivet13wactivet16sdatat16ht15dactivet13wIOWt16st16hD0 to D7002aaa334Fig 10.General write timing whenAS is tied to GNDIOWactivet17dRTSDTRchange of statechange of stateDCDCTSDSRt18dchange of statet18dchange of stateINTactivet19dactiveactiveIORactiveactivet18dactiveRIchange of state002aaa111Fig 11.Modem input/output timingSC16C750B_5© NXP B.V. 2008. All rights reserved.

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5 V, 3.3 V and 2.5 V UART with -byte FIFOs

tw2EXTERNALCLOCKtw3tw1002aaa1121fXTAL1=-------tw3Fig 12.External clock timingstartbitdata bits (0 to 7)D0D1D2D3D4D5D6D7paritybitstopbitnextdatastartbitRX5 data bits6 data bits7 data bitsINTt20dactivet21dIORactive16 baud rate clock002aaa113Fig 13.Receive timingSC16C750B_5© NXP B.V. 2008. All rights reserved.

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5 V, 3.3 V and 2.5 V UART with -byte FIFOs

startbitdata bits (0 to 7)D0D1D2D3D4D5D6D7paritybitstopbitnextdatastartbitRXt25dRXRDYactive datareadyt26dIORactive002aaa114Fig 14.Receive ready timing in non-FIFO modestartbitdata bits (0 to 7)D0D1D2D3D4D5D6D7paritybitstopbitRXfirst byte thatreaches thetrigger levelt25dRXRDYactive datareadyt26dIORactive002aaa115Fig 15.Receive ready timing in FIFO modeSC16C750B_5© NXP B.V. 2008. All rights reserved.

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5 V, 3.3 V and 2.5 V UART with -byte FIFOs

startbitdata bits (0 to 7)D0D1D2D3D4D5D6D7paritybitstopbitnextdatastartbitTX5 data bits6 data bits7 data bitsINTt22dt23dIOWactiveactivetransmitter readyt24dactive16 baud rate clock002aaa116Fig 16.Transmit timingstartbitdata bits (0 to 7)D0D1D2D3D4D5D6D7paritybitstopbitnextdatastartbitTXIOWactivetransmitter readyD0 to D7byte #1t28dt27dTXRDYactivetransmitternot ready002aaa129Fig 17.Transmit ready timing in non-FIFO modeSC16C750B_5© NXP B.V. 2008. All rights reserved.

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5 V, 3.3 V and 2.5 V UART with -byte FIFOs

startbitdata bits (0 to 7)D0D1D2D3D4D5D6D7paritybitstopbitTX5 data bits6 data bits7 data bitsIOWactivet28dD0 to D7byte #16or byte #t27dTXRDYFIFO full002aaa118Fig 18.Transmit ready timing in FIFO mode (DMA mode ‘1’)SC16C750B_5© NXP B.V. 2008. All rights reserved.

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5 V, 3.3 V and 2.5 V UART with -byte FIFOs

11.Package outline

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

eDyXAZEeE392928bpb1wM40441pin 1 indexEHEAA4A1(A )3eβk618Lp7eDHD17ZDBvMBvMAdetail X05scale10 mmDIMENSIONS (mm dimensions are derived from the original inch dimensions)A4A1eUNITAA3D(1)E(1)eDeEHDbpb1max.min.mm4.574.190.510.250.013.050.530.330.810.66HEkLp1.441.02v0.18w0.18y0.1ZD(1)ZE(1)max.max.2.162.16β16.6616.6616.0016.0017.6517.651.221.2716.5116.5114.9914.9917.4017.401.070.630.590.630.590.180inches0.020.1650.0210.0320.6560.6560.050.120.0130.0260.6500.6500.6950.6950.0480.0570.0070.0070.0040.0850.0850.6850.6850.0420.04045oNote1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINEVERSIONSOT187-2 REFERENCES IEC112E10 JEDECMS-018 JEITAEDR-7319EUROPEANPROJECTIONISSUE DATE99-12-2701-11-14Fig 19.Package outline SOT187-2 (PLCC44)

SC16C750B_5

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5 V, 3.3 V and 2.5 V UART with -byte FIFOs

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

DBAterminal 1index areaEAA1cdetail Xe1e9L817e1/2 eCb16vMCABwMCy1CyEh1/2 ee21terminal 1index area2432Dh02.5scaleE(1)5.14.9Eh3.252.95e0.5e13.5e23.5L0.50.3v0.1w0.05y0.05y10.15 mm25XDIMENSIONS (mm are the original dimensions)UNITmmA(1)max.1A10.050.00b0.300.18c0.2D(1)5.14.9Dh3.252.95Note1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINEVERSION SOT617-1 REFERENCES IEC- - - JEDECMO-220 JEITA- - -EUROPEANPROJECTIONISSUE DATE01-08-0802-10-18Fig 20.Package outline SOT617-1 (HVQFN32)

SC16C750B_5

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LQFP: plastic low profile quad flat package; leads; body 10 x 10 x 1.4 mmSOT314-2

cyXA48493332ZEeEHEwMθbp1pin 1 index16ZDvMA17detail XLLpAA2A1(A )3ebpDHDwMBvMB02.5scale5 mmDIMENSIONS (mm are the original dimensions)UNITmmAmax.1.6A10.200.05A21.451.35A30.25bp0.270.17c0.180.12D(1)10.19.9E(1)10.19.9e0.5HDHEL1Lp0.750.45v0.2w0.12y0.1ZD(1)ZE(1)1.451.051.451.05θ7oo012.1512.1511.8511.85Note1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINEVERSION SOT314-2 REFERENCES IEC136E10 JEDECMS-026 JEITAEUROPEANPROJECTIONISSUE DATE00-01-1903-02-25Fig 21.Package outline SOT314-2 (LQFP)

SC16C750B_5

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12.Soldering of SMD packages

Thistextprovidesaverybriefinsightintoacomplextechnology.Amorein-depthaccountof soldering ICs can be found in Application NoteAN10365 “Surface mount reﬂowsoldering description”.

12.1Introduction to soldering

Soldering is one of the most common methods through which packages are attached toPrintedCircuitBoards(PCBs),toformelectricalcircuits.Thesolderedjointprovidesboththe mechanical and the electrical connection. There is no single soldering method that isideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is notsuitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and highdensities that come with increased miniaturization.

12.2Wave and reﬂow soldering

Wavesolderingisajoiningtechnologyinwhichthejointsaremadebysoldercomingfroma standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadlesspackages which have solder lands underneath the body, cannot be wave soldered. Also,leaded SMDs with leads having a pitch smaller than ~0.6mm cannot be wave soldered,due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed bycomponent placement and exposure to a temperature proﬁle. Leaded packages,packages with solder balls, and leadless packages are all reﬂow solderable.Key characteristics in both wave and reﬂow soldering are:

••••••

Board speciﬁcations, including the board ﬁnish, solder masks and viasPackage footprints, including solder thieves and orientationThe moisture sensitivity level of the packagesPackage placementInspection and repair

Lead-free soldering versus SnPb soldering

12.3Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components areexposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

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5 V, 3.3 V and 2.5 V UART with -byte FIFOs

12.4Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-freeversusSnPbsoldering;notethatalead-freereﬂowprocessusuallyleadsto

higher minimum peak temperatures (seeFigure22) than a SnPb process, thusreducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperatureishighenoughforthesoldertomakereliablesolderjoints(asolderpastecharacteristic). In addition, the peak temperature must be low enough that thepackages and/or boards are not damaged. The peak temperature of the packagedepends on package thickness and volume and is classiﬁed in accordance withTable27 and28

Table 27.

SnPb eutectic process (from J-STD-020C)

Package reﬂow temperature (°C)Volume (mm3)< 350< 2.5≥ 2.5Table 28.

235220

Lead-free process (from J-STD-020C)

Package reﬂow temperature (°C)Volume (mm3)< 350< 1.61.6 to 2.5> 2.5

260260250

350 to 2000260250245

> 2000260245245

≥ 350220220

Package thickness (mm)Package thickness (mm)Moisture sensitivity precautions, as indicated on the packing, must be respected at alltimes.

Studies have shown that small packages reach higher temperatures during reﬂowsoldering, seeFigure22.

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temperaturemaximum peak temperature= MSL limit, damage levelminimum peak temperature= minimum soldering temperaturepeak temperaturetime001aac844MSL: Moisture Sensitivity LevelFig 22.Temperature proﬁles for large and small componentsFor further information on temperature proﬁles, refer to Application NoteAN10365“Surface mount reﬂow soldering description”.

13.Abbreviations

Table 29.AcronymCMOSCPUDLLDLMDMAFIFOISDNLSBMSBTTLUART

Abbreviations

DescriptionComplementary Metal Oxide SemiconductorCentral Processing UnitDivisor Latch LSBDivisor Latch MSBDirect Memory AccessFirst In, First Out

Integrated Service Digital NetworkLeast Signiﬁcant BitMost Signiﬁcant BitTransistor-Transistor Logic

Universal Asynchronous Receiver and Transmitter

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5 V, 3.3 V and 2.5 V UART with -byte FIFOs

14.Revision history

Table 30.

Revision history

Release date20081017

Data sheet statusProduct data sheet

Change notice-SupersedesSC16C750B_4

Document IDSC16C750B_5Modiﬁcations:

•••••••

The format of this data sheet has been redesigned to comply with the new identity guidelines ofNXP Semiconductors.

Legal texts have been adapted to the new company name where appropriate.Section 2 “Features”, 3rd bullet item re-written; addedFootnote 1

Figure 3 “Pin conﬁguration for HVQFN32”: corrected pin7 signal name from “CS2” to “CS”Table 2 “Pin description”, description ofRI: changed from “... has transitioned from a LOW to aHIGH ...” to “... has changed from a LOW to a HIGH ...”Table 24 “Limiting values”:

–symbol Vn split to show 2 separate conditions: “at D7 to D0 pins” and “at input only pins”Table 25 “Static characteristics”:

–Symbol/parameter changed from “VIL(CK), LOW-level clock input voltage” to “VIL(clk), clockLOW-level input voltage”–Symbol/parameter changed from “VIH(CK), HIGH-level clock input voltage” to “VIH(clk), clockHIGH-level input voltage”–Symbol changed from “ICL” to “IL(clk)”

–Table note [1]: changed from “Except for x2, ...” to “Except for XTAL2, ...”

••

SC16C750B_4

Table 26 “Dynamic characteristics”:

–Symbol “tw2, t2w” changed to 2 separate symbols, “tw1” and “tw2”

–Table note [4]: added “CS” to list of signals which must be inactive when reset pulse happensUpdated soldering information

Product data sheetProduct dataProduct dataProduct data

----SC16C750B-03SC16C750B-02SC16C750B-01-

20060825

SC16C750B-0320041213(939775014453)

SC16C750B-0220040527(939775013318)

SC16C750B-0120040329(939775011969)

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15.Legal information

15.1Data sheet status

Document status[1][2]Objective [short] data sheetPreliminary [short] data sheetProduct [short] data sheet

[1][2][3]

Product status[3]DevelopmentQualiﬁcationProduction

DeﬁnitionThis document contains data from the objective speciﬁcation for product development.This document contains data from the preliminary speciﬁcation.This document contains the product speciﬁcation.

Please consult the most recently issued document before initiating or completing a design.The term ‘short data sheet’ is explained in section “Deﬁnitions”.

Theproductstatusofdevice(s)describedinthisdocumentmayhavechangedsincethisdocumentwaspublishedandmaydifferincaseofmultipledevices.Thelatestproductstatusinformation is available on the Internet at URLhttp://www.nxp.com.

15.2Deﬁnitions

Draft —The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result inmodiﬁcations or additions. NXP Semiconductors does not give anyrepresentations or warranties as to the accuracy or completeness of

informationincludedhereinandshallhavenoliabilityfortheconsequencesofuse of such information.

Short data sheet —A short data sheet is an extract from a full data sheetwiththesameproducttypenumber(s)andtitle.Ashortdatasheetisintendedforquickreferenceonlyandshouldnotbereliedupontocontaindetailedandfull information. For detailed and full information see the relevant full datasheet, which is available on request via the local NXP Semiconductors salesofﬁce. In case of any inconsistency or conﬂict with the short data sheet, thefull data sheet shall prevail.

malfunction of an NXP Semiconductors product can reasonably be expectedto result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use ofNXP Semiconductors products in such equipment or applications andtherefore such inclusion and/or use is at the customer’s own risk.

Applications —Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for thespeciﬁed use without further testing or modiﬁcation.

Limiting values —Stress above one or more limiting values (as deﬁned intheAbsoluteMaximumRatingsSystemofIEC60134)maycausepermanentdamagetothedevice.Limitingvaluesarestressratingsonlyandoperationofthe device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limitingvalues for extended periods may affect device reliability.

Terms and conditions of sale —NXP Semiconductors products are soldsubjecttothegeneraltermsandconditionsofcommercialsale,aspublishedathttp://www.nxp.com/proﬁle/terms, including those pertaining to warranty,intellectual property rights infringement and limitation of liability, unlessexplicitly otherwise agreed to in writing by NXP Semiconductors. In case ofany inconsistency or conﬂict between information in this document and suchterms and conditions, the latter will prevail.

No offer to sell or license —Nothing in this document may be interpretedor construed as an offer to sell products that is open for acceptance or thegrant,conveyanceorimplicationofanylicenseunderanycopyrights,patentsor other industrial or intellectual property rights.

15.3Disclaimers

General —Information in this document is believed to be accurate and

reliable.However,NXPSemiconductorsdoesnotgiveanyrepresentationsorwarranties,expressedorimplied,astotheaccuracyorcompletenessofsuchinformation and shall have no liability for the consequences of use of suchinformation.

Right to make changes —NXPSemiconductorsreservestherighttomakechanges to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and withoutnotice.Thisdocumentsupersedesandreplacesallinformationsuppliedpriorto the publication hereof.

Suitability for use —NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure or

15.4Trademarks

Notice:Allreferencedbrands,productnames,servicenamesandtrademarksare the property of their respective owners.

16.Contact information

For more information, please visit:http://www.nxp.com

For sales ofﬁce addresses, please send an email to:salesaddresses@nxp.com

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17.Contents

1General description. . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Ordering information. . . . . . . . . . . . . . . . . . . . . 24Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 35Pinning information. . . . . . . . . . . . . . . . . . . . . . 45.1Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 56Functional description . . . . . . . . . . . . . . . . . . . 86.1Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 96.2FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 106.3Hardware ﬂow control. . . . . . . . . . . . . . . . . . . 106.4Time-out interrupts. . . . . . . . . . . . . . . . . . . . . 106.5Programmable baud rate generator . . . . . . . . 116.6DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 126.7Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 136.8Low power mode . . . . . . . . . . . . . . . . . . . . . . 136.9Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 137Register descriptions . . . . . . . . . . . . . . . . . . . 157.1

Transmit Holding Register (THR) and

Receive Holding Register (RHR) . . . . . . . . . . 16

7.2Interrupt Enable Register (IER) . . . . . . . . . . . 167.2.1IER versus Receive FIFO interrupt mode

operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.2.2IER versus Receive/Transmit FIFO polled

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 17

7.3FIFO Control Register (FCR) . . . . . . . . . . . . . 187.3.1DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 187.3.1.1Mode 0 (FCR bit 3=0). . . . . . . . . . . . . . . . . . 187.3.1.2Mode 1 (FCR bit 3=1). . . . . . . . . . . . . . . . . . 187.3.2FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 187.4Interrupt Status Register (ISR). . . . . . . . . . . . 207.5Line Control Register (LCR). . . . . . . . . . . . . . 217.6Modem Control Register (MCR). . . . . . . . . . . 237.7Line Status Register (LSR). . . . . . . . . . . . . . . 247.8Modem Status Register (MSR). . . . . . . . . . . . 257.9Scratchpad Register (SPR) . . . . . . . . . . . . . . 267.10SC16C750B external reset conditions . . . . . . 268Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 269Static characteristics. . . . . . . . . . . . . . . . . . . . 2710Dynamic characteristics . . . . . . . . . . . . . . . . . 2810.1Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 2911Package outline . . . . . . . . . . . . . . . . . . . . . . . . 3612Soldering of SMD packages . . . . . . . . . . . . . . 3912.1Introduction to soldering. . . . . . . . . . . . . . . . . 3912.2Wave and reﬂow soldering . . . . . . . . . . . . . . . 3912.3Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 39

SC16C750B

5 V, 3.3 V and 2.5 V UART with -byte FIFOs

12.4

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 4013Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 4114Revision history . . . . . . . . . . . . . . . . . . . . . . . 4215Legal information . . . . . . . . . . . . . . . . . . . . . . 4315.1Data sheet status. . . . . . . . . . . . . . . . . . . . . . 4315.2Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4315.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 4315.4Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 4316Contact information . . . . . . . . . . . . . . . . . . . . 4317

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pleasebeawarethatimportantnoticesconcerningthisdocumentandtheproduct(s)described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 17 October 2008Document identifier: SC16C750B_5

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