(1)时钟div2clock是clock的两倍分频
#Constrain the base clock
create_clock -add -period 10.000 \
-waveform { 0.000 5.000 } \
-name clock_name \
[get_ports clock]
#Constrain the divide by 2 register clock
create_generated_clock -add -source clock \
-name div2clock \
-divide_by 2 \
-master_clock clock_name \
[get_pins div2reg|regout]
(2)时钟clock_name从PLL中2倍倍频得到PLL_inst|CLK[1]
#Constrain the base clock
create_clock -add -period 10.000 \
-waveform { 0.000 5.000 } \
-name clock_name \
[get_ports clock]
#Constrain the output clock clock
create_generated_clock -add -source PLL_inst|INCLK[0] \
-name PLL_inst|CLK[1] \
-multiply_by 2 \
-master_clock clock_name \
[get_pins PLL_inst|CLK[1]]
